Tri Vo 6e8abbc8b9 [AArch64] Support reserving x1-7 registers. ...

Summary: Reserving registers x1-7 is used to support CONFIG_ARM64_LSE_ATOMICS in Linux kernel. This change adds support for reserving registers x1 through x7.

Reviewers: javed.absar, efriedma, nickdesaulniers, srhines, phosek

Reviewed By: nickdesaulniers

Subscribers: manojgupta, jfb, cfe-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D48581

llvm-svn: 342100

2018-09-12 23:45:04 +00:00

..

AArch64.cpp

[AArch64] Support reserving x1-7 registers.

2018-09-12 23:45:04 +00:00

AArch64.h

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ARM.cpp

OpenBSD/arm has switched to float ABI SoftFP.

2018-07-22 21:39:54 +00:00

ARM.h

[ARM] Option for reading thread pointer from coprocessor register

2017-09-12 10:40:58 +00:00

Mips.cpp

[mips] Add '-mvirt', '-mno-virt', '-mginv', '-mno-ginv' options

2018-07-11 12:45:25 +00:00

Mips.h

Use Triple::isMIPS() instead of enumerating all Triples. NFC

2018-06-25 16:49:52 +00:00

PPC.cpp

[PowerPC] Option for secure plt mode

2018-04-11 12:24:44 +00:00

PPC.h

Change \t to spaces

2018-07-20 08:19:20 +00:00

RISCV.cpp

Remove trailing space

2018-07-30 19:24:48 +00:00

RISCV.h

[RISCV] Add the RISCV target and compiler driver

2018-01-11 13:36:56 +00:00

Sparc.cpp

[Sparc] Use the leon arch for Leon3's when using an external assembler

2018-05-24 06:16:02 +00:00

Sparc.h

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SystemZ.cpp

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SystemZ.h

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X86.cpp

[x86/SLH] Add a real Clang flag and LLVM IR attribute for Speculative

2018-09-04 12:38:00 +00:00

X86.h

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