57f661bd7d
On targets like Arm some relaxations may only be performed when certain architectural features are available. As functions can be compiled with differing levels of architectural support we must make a judgement on whether we can relax based on the MCSubtargetInfo for the function. This change passes through the MCSubtargetInfo for the function to fixupNeedsRelaxation so that the decision on whether to relax can be made per function. In this patch, only the ARM backend makes use of this information. We must also pass the MCSubtargetInfo to applyFixup because some fixups skip error checking on the assumption that relaxation has occurred, to prevent code-generation errors applyFixup must see the same MCSubtargetInfo as fixupNeedsRelaxation. Differential Revision: https://reviews.llvm.org/D44928 llvm-svn: 334078
98 lines
3.1 KiB
C++
98 lines
3.1 KiB
C++
//===-- MipsAsmBackend.h - Mips Asm Backend ------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the MipsAsmBackend class.
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//
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//===----------------------------------------------------------------------===//
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//
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#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSASMBACKEND_H
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#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSASMBACKEND_H
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#include "MCTargetDesc/MipsFixupKinds.h"
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#include "llvm/ADT/Triple.h"
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#include "llvm/MC/MCAsmBackend.h"
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namespace llvm {
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class MCAssembler;
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struct MCFixupKindInfo;
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class MCObjectWriter;
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class MCRegisterInfo;
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class Target;
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class MipsAsmBackend : public MCAsmBackend {
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Triple TheTriple;
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bool IsN32;
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public:
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MipsAsmBackend(const Target &T, const MCRegisterInfo &MRI, const Triple &TT,
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StringRef CPU, bool N32)
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: MCAsmBackend(TT.isLittleEndian() ? support::little : support::big),
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TheTriple(TT), IsN32(N32) {}
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std::unique_ptr<MCObjectTargetWriter>
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createObjectTargetWriter() const override;
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void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCValue &Target, MutableArrayRef<char> Data,
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uint64_t Value, bool IsResolved,
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const MCSubtargetInfo *STI) const override;
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Optional<MCFixupKind> getFixupKind(StringRef Name) const override;
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const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override;
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unsigned getNumFixupKinds() const override {
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return Mips::NumTargetFixupKinds;
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}
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/// @name Target Relaxation Interfaces
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/// @{
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/// MayNeedRelaxation - Check whether the given instruction may need
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/// relaxation.
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///
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/// \param Inst - The instruction to test.
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bool mayNeedRelaxation(const MCInst &Inst,
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const MCSubtargetInfo &STI) const override {
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return false;
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}
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/// fixupNeedsRelaxation - Target specific predicate for whether a given
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/// fixup requires the associated instruction to be relaxed.
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bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
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const MCRelaxableFragment *DF,
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const MCAsmLayout &Layout) const override {
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// FIXME.
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llvm_unreachable("RelaxInstruction() unimplemented");
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return false;
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}
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/// RelaxInstruction - Relax the instruction in the given fragment
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/// to the next wider instruction.
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///
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/// \param Inst - The instruction to relax, which may be the same
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/// as the output.
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/// \param [out] Res On return, the relaxed instruction.
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void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI,
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MCInst &Res) const override {}
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/// @}
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bool writeNopData(raw_ostream &OS, uint64_t Count) const override;
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bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCValue &Target) override;
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}; // class MipsAsmBackend
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} // namespace
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#endif
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