65d463bdd7
Lower integer arguments smaller than i32. Support both register and stack arguments. Define setLocInfo function for setting LocInfo field in ArgLocs vector. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D51031 llvm-svn: 340572
538 lines
18 KiB
C++
538 lines
18 KiB
C++
//===- MipsCallLowering.cpp -------------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// This file implements the lowering of LLVM calls to machine code calls for
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/// GlobalISel.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsCallLowering.h"
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#include "MipsCCState.h"
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#include "MipsTargetMachine.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
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using namespace llvm;
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MipsCallLowering::MipsCallLowering(const MipsTargetLowering &TLI)
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: CallLowering(&TLI) {}
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bool MipsCallLowering::MipsHandler::assign(unsigned VReg,
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const CCValAssign &VA) {
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if (VA.isRegLoc()) {
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assignValueToReg(VReg, VA);
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} else if (VA.isMemLoc()) {
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assignValueToAddress(VReg, VA);
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} else {
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return false;
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}
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return true;
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}
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namespace {
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class IncomingValueHandler : public MipsCallLowering::MipsHandler {
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public:
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IncomingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI)
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: MipsHandler(MIRBuilder, MRI) {}
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bool handle(ArrayRef<CCValAssign> ArgLocs,
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ArrayRef<CallLowering::ArgInfo> Args);
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private:
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void assignValueToReg(unsigned ValVReg, const CCValAssign &VA) override;
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unsigned getStackAddress(const CCValAssign &VA,
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MachineMemOperand *&MMO) override;
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void assignValueToAddress(unsigned ValVReg, const CCValAssign &VA) override;
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virtual void markPhysRegUsed(unsigned PhysReg) {
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MIRBuilder.getMBB().addLiveIn(PhysReg);
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}
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void buildLoad(unsigned Val, const CCValAssign &VA) {
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MachineMemOperand *MMO;
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unsigned Addr = getStackAddress(VA, MMO);
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MIRBuilder.buildLoad(Val, Addr, *MMO);
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}
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};
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class CallReturnHandler : public IncomingValueHandler {
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public:
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CallReturnHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
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MachineInstrBuilder &MIB)
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: IncomingValueHandler(MIRBuilder, MRI), MIB(MIB) {}
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private:
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void markPhysRegUsed(unsigned PhysReg) override {
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MIB.addDef(PhysReg, RegState::Implicit);
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}
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MachineInstrBuilder &MIB;
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};
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} // end anonymous namespace
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void IncomingValueHandler::assignValueToReg(unsigned ValVReg,
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const CCValAssign &VA) {
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unsigned PhysReg = VA.getLocReg();
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switch (VA.getLocInfo()) {
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case CCValAssign::LocInfo::SExt:
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case CCValAssign::LocInfo::ZExt:
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case CCValAssign::LocInfo::AExt: {
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auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
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MIRBuilder.buildTrunc(ValVReg, Copy);
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break;
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}
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default:
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MIRBuilder.buildCopy(ValVReg, PhysReg);
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break;
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}
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markPhysRegUsed(PhysReg);
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}
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unsigned IncomingValueHandler::getStackAddress(const CCValAssign &VA,
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MachineMemOperand *&MMO) {
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unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
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unsigned Offset = VA.getLocMemOffset();
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MachineFrameInfo &MFI = MIRBuilder.getMF().getFrameInfo();
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int FI = MFI.CreateFixedObject(Size, Offset, true);
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MachinePointerInfo MPO =
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MachinePointerInfo::getFixedStack(MIRBuilder.getMF(), FI);
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MMO = MIRBuilder.getMF().getMachineMemOperand(MPO, MachineMemOperand::MOLoad,
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Size, /* Alignment */ 0);
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unsigned AddrReg = MRI.createGenericVirtualRegister(LLT::pointer(0, 32));
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MIRBuilder.buildFrameIndex(AddrReg, FI);
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return AddrReg;
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}
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void IncomingValueHandler::assignValueToAddress(unsigned ValVReg,
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const CCValAssign &VA) {
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if (VA.getLocInfo() == CCValAssign::SExt ||
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VA.getLocInfo() == CCValAssign::ZExt ||
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VA.getLocInfo() == CCValAssign::AExt) {
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unsigned LoadReg = MRI.createGenericVirtualRegister(LLT::scalar(32));
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buildLoad(LoadReg, VA);
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MIRBuilder.buildTrunc(ValVReg, LoadReg);
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} else
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buildLoad(ValVReg, VA);
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}
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bool IncomingValueHandler::handle(ArrayRef<CCValAssign> ArgLocs,
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ArrayRef<CallLowering::ArgInfo> Args) {
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for (unsigned i = 0, ArgsSize = Args.size(); i < ArgsSize; ++i) {
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if (!assign(Args[i].Reg, ArgLocs[i]))
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return false;
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}
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return true;
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}
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namespace {
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class OutgoingValueHandler : public MipsCallLowering::MipsHandler {
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public:
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OutgoingValueHandler(MachineIRBuilder &MIRBuilder, MachineRegisterInfo &MRI,
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MachineInstrBuilder &MIB)
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: MipsHandler(MIRBuilder, MRI), MIB(MIB) {}
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bool handle(ArrayRef<CCValAssign> ArgLocs,
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ArrayRef<CallLowering::ArgInfo> Args);
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private:
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void assignValueToReg(unsigned ValVReg, const CCValAssign &VA) override;
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unsigned getStackAddress(const CCValAssign &VA,
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MachineMemOperand *&MMO) override;
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void assignValueToAddress(unsigned ValVReg, const CCValAssign &VA) override;
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unsigned extendRegister(unsigned ValReg, const CCValAssign &VA);
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MachineInstrBuilder &MIB;
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};
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} // end anonymous namespace
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void OutgoingValueHandler::assignValueToReg(unsigned ValVReg,
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const CCValAssign &VA) {
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unsigned PhysReg = VA.getLocReg();
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unsigned ExtReg = extendRegister(ValVReg, VA);
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MIRBuilder.buildCopy(PhysReg, ExtReg);
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MIB.addUse(PhysReg, RegState::Implicit);
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}
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unsigned OutgoingValueHandler::getStackAddress(const CCValAssign &VA,
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MachineMemOperand *&MMO) {
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LLT p0 = LLT::pointer(0, 32);
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LLT s32 = LLT::scalar(32);
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unsigned SPReg = MRI.createGenericVirtualRegister(p0);
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MIRBuilder.buildCopy(SPReg, Mips::SP);
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unsigned OffsetReg = MRI.createGenericVirtualRegister(s32);
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unsigned Offset = VA.getLocMemOffset();
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MIRBuilder.buildConstant(OffsetReg, Offset);
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unsigned AddrReg = MRI.createGenericVirtualRegister(p0);
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MIRBuilder.buildGEP(AddrReg, SPReg, OffsetReg);
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MachinePointerInfo MPO =
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MachinePointerInfo::getStack(MIRBuilder.getMF(), Offset);
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unsigned Size = alignTo(VA.getValVT().getSizeInBits(), 8) / 8;
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MMO = MIRBuilder.getMF().getMachineMemOperand(MPO, MachineMemOperand::MOStore,
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Size, /* Alignment */ 0);
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return AddrReg;
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}
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void OutgoingValueHandler::assignValueToAddress(unsigned ValVReg,
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const CCValAssign &VA) {
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MachineMemOperand *MMO;
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unsigned Addr = getStackAddress(VA, MMO);
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unsigned ExtReg = extendRegister(ValVReg, VA);
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MIRBuilder.buildStore(ExtReg, Addr, *MMO);
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}
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unsigned OutgoingValueHandler::extendRegister(unsigned ValReg,
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const CCValAssign &VA) {
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LLT LocTy{VA.getLocVT()};
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switch (VA.getLocInfo()) {
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case CCValAssign::SExt: {
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unsigned ExtReg = MRI.createGenericVirtualRegister(LocTy);
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MIRBuilder.buildSExt(ExtReg, ValReg);
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return ExtReg;
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}
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case CCValAssign::ZExt: {
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unsigned ExtReg = MRI.createGenericVirtualRegister(LocTy);
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MIRBuilder.buildZExt(ExtReg, ValReg);
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return ExtReg;
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}
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case CCValAssign::AExt: {
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unsigned ExtReg = MRI.createGenericVirtualRegister(LocTy);
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MIRBuilder.buildAnyExt(ExtReg, ValReg);
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return ExtReg;
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}
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// TODO : handle upper extends
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case CCValAssign::Full:
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return ValReg;
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default:
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break;
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}
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llvm_unreachable("unable to extend register");
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}
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bool OutgoingValueHandler::handle(ArrayRef<CCValAssign> ArgLocs,
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ArrayRef<CallLowering::ArgInfo> Args) {
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for (unsigned i = 0; i < Args.size(); ++i) {
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if (!assign(Args[i].Reg, ArgLocs[i]))
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return false;
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}
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return true;
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}
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static bool isSupportedType(Type *T) {
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if (T->isIntegerTy() && T->getScalarSizeInBits() <= 32)
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return true;
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if (T->isPointerTy())
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return true;
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return false;
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}
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CCValAssign::LocInfo determineLocInfo(const MVT RegisterVT, const EVT VT,
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const ISD::ArgFlagsTy &Flags) {
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if (VT.getSizeInBits() == RegisterVT.getSizeInBits())
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return CCValAssign::LocInfo::Full;
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if (Flags.isSExt())
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return CCValAssign::LocInfo::SExt;
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if (Flags.isZExt())
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return CCValAssign::LocInfo::ZExt;
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return CCValAssign::LocInfo::AExt;
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}
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template <typename T>
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void setLocInfo(SmallVectorImpl<CCValAssign> &ArgLocs,
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const SmallVectorImpl<T> &Arguments) {
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for (unsigned i = 0; i < ArgLocs.size(); ++i) {
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const CCValAssign &VA = ArgLocs[i];
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CCValAssign::LocInfo LocInfo = determineLocInfo(
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Arguments[i].VT, Arguments[i].ArgVT, Arguments[i].Flags);
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if (VA.isMemLoc())
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ArgLocs[i] =
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CCValAssign::getMem(VA.getValNo(), VA.getValVT(),
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VA.getLocMemOffset(), VA.getLocVT(), LocInfo);
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else
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ArgLocs[i] = CCValAssign::getReg(VA.getValNo(), VA.getValVT(),
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VA.getLocReg(), VA.getLocVT(), LocInfo);
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}
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}
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bool MipsCallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
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const Value *Val,
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ArrayRef<unsigned> VRegs) const {
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MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(Mips::RetRA);
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if (Val != nullptr && !isSupportedType(Val->getType()))
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return false;
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if (!VRegs.empty()) {
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = MF.getFunction();
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const DataLayout &DL = MF.getDataLayout();
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const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
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LLVMContext &Ctx = Val->getType()->getContext();
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SmallVector<EVT, 4> SplitEVTs;
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ComputeValueVTs(TLI, DL, Val->getType(), SplitEVTs);
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assert(VRegs.size() == SplitEVTs.size() &&
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"For each split Type there should be exactly one VReg.");
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SmallVector<ArgInfo, 8> RetInfos;
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SmallVector<unsigned, 8> OrigArgIndices;
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for (unsigned i = 0; i < SplitEVTs.size(); ++i) {
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ArgInfo CurArgInfo = ArgInfo{VRegs[i], SplitEVTs[i].getTypeForEVT(Ctx)};
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setArgFlags(CurArgInfo, AttributeList::ReturnIndex, DL, F);
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splitToValueTypes(CurArgInfo, 0, RetInfos, OrigArgIndices);
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}
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SmallVector<ISD::OutputArg, 8> Outs;
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subTargetRegTypeForCallingConv(
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MIRBuilder, RetInfos, OrigArgIndices,
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[&](ISD::ArgFlagsTy flags, EVT vt, EVT argvt, bool used,
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unsigned origIdx, unsigned partOffs) {
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Outs.emplace_back(flags, vt, argvt, used, origIdx, partOffs);
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});
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SmallVector<CCValAssign, 16> ArgLocs;
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MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
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F.getContext());
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CCInfo.AnalyzeReturn(Outs, TLI.CCAssignFnForReturn());
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setLocInfo(ArgLocs, Outs);
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OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), Ret);
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if (!RetHandler.handle(ArgLocs, RetInfos)) {
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return false;
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}
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}
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MIRBuilder.insertInstr(Ret);
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return true;
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}
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bool MipsCallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
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const Function &F,
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ArrayRef<unsigned> VRegs) const {
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// Quick exit if there aren't any args.
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if (F.arg_empty())
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return true;
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if (F.isVarArg()) {
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return false;
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}
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for (auto &Arg : F.args()) {
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if (!isSupportedType(Arg.getType()))
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return false;
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}
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MachineFunction &MF = MIRBuilder.getMF();
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const DataLayout &DL = MF.getDataLayout();
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const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
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SmallVector<ArgInfo, 8> ArgInfos;
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SmallVector<unsigned, 8> OrigArgIndices;
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unsigned i = 0;
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for (auto &Arg : F.args()) {
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ArgInfo AInfo(VRegs[i], Arg.getType());
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setArgFlags(AInfo, i + AttributeList::FirstArgIndex, DL, F);
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splitToValueTypes(AInfo, i, ArgInfos, OrigArgIndices);
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++i;
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}
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SmallVector<ISD::InputArg, 8> Ins;
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subTargetRegTypeForCallingConv(
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MIRBuilder, ArgInfos, OrigArgIndices,
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[&](ISD::ArgFlagsTy flags, EVT vt, EVT argvt, bool used, unsigned origIdx,
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unsigned partOffs) {
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Ins.emplace_back(flags, vt, argvt, used, origIdx, partOffs);
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});
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SmallVector<CCValAssign, 16> ArgLocs;
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MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
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F.getContext());
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const MipsTargetMachine &TM =
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static_cast<const MipsTargetMachine &>(MF.getTarget());
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const MipsABIInfo &ABI = TM.getABI();
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CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(F.getCallingConv()),
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1);
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CCInfo.AnalyzeFormalArguments(Ins, TLI.CCAssignFnForCall());
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setLocInfo(ArgLocs, Ins);
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IncomingValueHandler Handler(MIRBuilder, MF.getRegInfo());
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if (!Handler.handle(ArgLocs, ArgInfos))
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return false;
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return true;
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}
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bool MipsCallLowering::lowerCall(MachineIRBuilder &MIRBuilder,
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CallingConv::ID CallConv,
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const MachineOperand &Callee,
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const ArgInfo &OrigRet,
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ArrayRef<ArgInfo> OrigArgs) const {
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if (CallConv != CallingConv::C)
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return false;
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for (auto &Arg : OrigArgs) {
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if (!isSupportedType(Arg.Ty))
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return false;
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if (Arg.Flags.isByVal() || Arg.Flags.isSRet())
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return false;
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}
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if (OrigRet.Reg && !isSupportedType(OrigRet.Ty))
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return false;
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MachineFunction &MF = MIRBuilder.getMF();
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const Function &F = MF.getFunction();
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const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
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const MipsTargetMachine &TM =
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static_cast<const MipsTargetMachine &>(MF.getTarget());
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const MipsABIInfo &ABI = TM.getABI();
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MachineInstrBuilder CallSeqStart =
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MIRBuilder.buildInstr(Mips::ADJCALLSTACKDOWN);
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// FIXME: Add support for pic calling sequences, long call sequences for O32,
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// N32 and N64. First handle the case when Callee.isReg().
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if (Callee.isReg())
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return false;
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MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(Mips::JAL);
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MIB.addDef(Mips::SP, RegState::Implicit);
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MIB.add(Callee);
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const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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MIB.addRegMask(TRI->getCallPreservedMask(MF, F.getCallingConv()));
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TargetLowering::ArgListTy FuncOrigArgs;
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FuncOrigArgs.reserve(OrigArgs.size());
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SmallVector<ArgInfo, 8> ArgInfos;
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SmallVector<unsigned, 8> OrigArgIndices;
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unsigned i = 0;
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for (auto &Arg : OrigArgs) {
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TargetLowering::ArgListEntry Entry;
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Entry.Ty = Arg.Ty;
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FuncOrigArgs.push_back(Entry);
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splitToValueTypes(Arg, i, ArgInfos, OrigArgIndices);
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++i;
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}
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SmallVector<ISD::OutputArg, 8> Outs;
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subTargetRegTypeForCallingConv(
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MIRBuilder, ArgInfos, OrigArgIndices,
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[&](ISD::ArgFlagsTy flags, EVT vt, EVT argvt, bool used, unsigned origIdx,
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unsigned partOffs) {
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Outs.emplace_back(flags, vt, argvt, used, origIdx, partOffs);
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});
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SmallVector<CCValAssign, 8> ArgLocs;
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MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
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F.getContext());
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CCInfo.AllocateStack(ABI.GetCalleeAllocdArgSizeInBytes(CallConv), 1);
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const char *Call = Callee.isSymbol() ? Callee.getSymbolName() : nullptr;
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CCInfo.AnalyzeCallOperands(Outs, TLI.CCAssignFnForCall(), FuncOrigArgs, Call);
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setLocInfo(ArgLocs, Outs);
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OutgoingValueHandler RetHandler(MIRBuilder, MF.getRegInfo(), MIB);
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if (!RetHandler.handle(ArgLocs, ArgInfos)) {
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return false;
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}
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unsigned NextStackOffset = CCInfo.getNextStackOffset();
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const TargetFrameLowering *TFL = MF.getSubtarget().getFrameLowering();
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unsigned StackAlignment = TFL->getStackAlignment();
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NextStackOffset = alignTo(NextStackOffset, StackAlignment);
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CallSeqStart.addImm(NextStackOffset).addImm(0);
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MIRBuilder.insertInstr(MIB);
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if (OrigRet.Reg) {
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ArgInfos.clear();
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SmallVector<unsigned, 8> OrigRetIndices;
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splitToValueTypes(OrigRet, 0, ArgInfos, OrigRetIndices);
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SmallVector<ISD::InputArg, 8> Ins;
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subTargetRegTypeForCallingConv(
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MIRBuilder, ArgInfos, OrigRetIndices,
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[&](ISD::ArgFlagsTy flags, EVT vt, EVT argvt, bool used,
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unsigned origIdx, unsigned partOffs) {
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Ins.emplace_back(flags, vt, argvt, used, origIdx, partOffs);
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});
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|
|
|
SmallVector<CCValAssign, 8> ArgLocs;
|
|
MipsCCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs,
|
|
F.getContext());
|
|
|
|
CCInfo.AnalyzeCallResult(Ins, TLI.CCAssignFnForReturn(), OrigRet.Ty, Call);
|
|
setLocInfo(ArgLocs, Ins);
|
|
|
|
CallReturnHandler Handler(MIRBuilder, MF.getRegInfo(), MIB);
|
|
if (!Handler.handle(ArgLocs, ArgInfos))
|
|
return false;
|
|
}
|
|
|
|
MIRBuilder.buildInstr(Mips::ADJCALLSTACKUP).addImm(NextStackOffset).addImm(0);
|
|
|
|
return true;
|
|
}
|
|
|
|
void MipsCallLowering::subTargetRegTypeForCallingConv(
|
|
MachineIRBuilder &MIRBuilder, ArrayRef<ArgInfo> Args,
|
|
ArrayRef<unsigned> OrigArgIndices, const FunTy &PushBack) const {
|
|
MachineFunction &MF = MIRBuilder.getMF();
|
|
const Function &F = MF.getFunction();
|
|
const DataLayout &DL = F.getParent()->getDataLayout();
|
|
const MipsTargetLowering &TLI = *getTLI<MipsTargetLowering>();
|
|
|
|
unsigned ArgNo = 0;
|
|
for (auto &Arg : Args) {
|
|
|
|
EVT VT = TLI.getValueType(DL, Arg.Ty);
|
|
MVT RegisterVT = TLI.getRegisterTypeForCallingConv(F.getContext(),
|
|
F.getCallingConv(), VT);
|
|
|
|
ISD::ArgFlagsTy Flags = Arg.Flags;
|
|
Flags.setOrigAlign(TLI.getABIAlignmentForCallingConv(Arg.Ty, DL));
|
|
|
|
PushBack(Flags, RegisterVT, VT, true, OrigArgIndices[ArgNo], 0);
|
|
|
|
++ArgNo;
|
|
}
|
|
}
|
|
|
|
void MipsCallLowering::splitToValueTypes(
|
|
const ArgInfo &OrigArg, unsigned OriginalIndex,
|
|
SmallVectorImpl<ArgInfo> &SplitArgs,
|
|
SmallVectorImpl<unsigned> &SplitArgsOrigIndices) const {
|
|
|
|
// TODO : perform structure and array split. For now we only deal with
|
|
// types that pass isSupportedType check.
|
|
SplitArgs.push_back(OrigArg);
|
|
SplitArgsOrigIndices.push_back(OriginalIndex);
|
|
}
|