Benjamin Kramer 27c769d28a [Target] Untangle disassemblers ...

Disassemblers cannot depend on main target headers. The same is true for
MCTargetDesc, but there's a lot more cleanup needed for that.

llvm-svn: 341822

2018-09-10 12:53:46 +00:00

..

AsmParser

[RISCV] Fixed SmallVector.h Assertion `idx < size()'

2018-08-30 19:43:19 +00:00

Disassembler

[RISCV] Fix crash in decoding instruction with unknown floating point rounding mode

2018-09-07 18:43:43 +00:00

InstPrinter

[RISCV] Tablegen-driven Instruction Compression.

2018-04-06 21:07:05 +00:00

MCTargetDesc

[Target] Untangle disassemblers

2018-09-10 12:53:46 +00:00

TargetInfo

…

CMakeLists.txt

[RISCV] Add machine function pass to merge base + offset

2018-06-27 20:51:42 +00:00

LLVMBuild.txt

…

RISCV.h

[RISCV] Add machine function pass to merge base + offset

2018-06-27 20:51:42 +00:00

RISCV.td

[RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation

2018-05-15 01:28:50 +00:00

RISCVAsmPrinter.cpp

Revert "[RISCV] implement li pseudo instruction"

2018-04-18 19:02:31 +00:00

RISCVCallingConv.td

[RISCV] Add support for _interrupt attribute

2018-07-26 17:49:43 +00:00

RISCVFrameLowering.cpp

[RISCV] Fix std::advance slowness

2018-08-24 23:13:59 +00:00

RISCVFrameLowering.h

…

RISCVInstrFormats.td

[RISCV] AsmParser support for the li pseudo instruction

2018-06-07 15:35:47 +00:00

RISCVInstrFormatsC.td

…

RISCVInstrInfo.cpp

[RISCV] Add support for _interrupt attribute

2018-07-26 17:49:43 +00:00

RISCVInstrInfo.h

[RISCV] Implement isLoadFromStackSlot and isStoreToStackSlot

2018-04-26 15:34:27 +00:00

RISCVInstrInfo.td

[RISCV] Add "lla" pseudo-instruction to assembler

2018-08-09 07:08:20 +00:00

RISCVInstrInfoA.td

[RISCV] atomic_store_nn have a different layout to regular store

2018-08-27 07:08:18 +00:00

RISCVInstrInfoC.td

[RISC-V] Fixed alias for addi x2, x2, 0

2018-08-09 20:51:53 +00:00

RISCVInstrInfoD.td

[RISCV] Add InstAlias definitions for fgt.{s|d}, fge.{s|d}

2018-06-20 14:03:02 +00:00

RISCVInstrInfoF.td

[RISCV] Fix crash in decoding instruction with unknown floating point rounding mode

2018-09-07 18:43:43 +00:00

RISCVInstrInfoM.td

…

RISCVISelDAGToDAG.cpp

[RISCV] Add machine function pass to merge base + offset

2018-06-27 20:51:42 +00:00

RISCVISelLowering.cpp

[RISCV] Remove unused function

2018-08-17 13:40:03 +00:00

RISCVISelLowering.h

[RISCV] Remove unused function

2018-08-17 13:40:03 +00:00

RISCVMachineFunctionInfo.h

[RISCV] Codegen support for RV32D floating point load/store, fadd.d, calling conv

2018-04-12 05:34:25 +00:00

RISCVMCInstLower.cpp

[RISCV] Add codegen for RV32F floating point load/store

2018-03-20 13:26:12 +00:00

RISCVMergeBaseOffset.cpp

Test commit.

2018-08-02 05:38:18 +00:00

RISCVRegisterInfo.cpp

[RISCV] Add support for _interrupt attribute

2018-07-26 17:49:43 +00:00

RISCVRegisterInfo.h

[RISCV] Set isReMaterializable on ADDI and LUI instructions

2018-05-17 15:51:37 +00:00

RISCVRegisterInfo.td

[RISCV] Lower the tail pseudoinstruction

2018-05-23 22:44:08 +00:00

RISCVSubtarget.cpp

…

RISCVSubtarget.h

[RISCV] Define FeatureRelax and shouldForceRelocation for RISCV linker relaxation

2018-05-15 01:28:50 +00:00

RISCVTargetMachine.cpp

[RISCV] Add machine function pass to merge base + offset

2018-06-27 20:51:42 +00:00

RISCVTargetMachine.h

…

RISCVTargetObjectFile.cpp

[RISCV] Use init_array instead of ctors for RISCV target, by default

2018-03-24 18:37:19 +00:00

RISCVTargetObjectFile.h

[RISCV] Use init_array instead of ctors for RISCV target, by default

2018-03-24 18:37:19 +00:00