9eaf5aa006
This patch removes redundant template argument `TargetName` from TIIPredicate. Tablegen can always infer the target name from the context. So we don't need to force users of TIIPredicate to always specify it. This allows us to better modularize the tablegen class hierarchy for the so-called "function predicates". class FunctionPredicateBase has been added; it is currently used as a building block for TIIPredicates. However, I plan to reuse that class to model other function predicate classes too (i.e. not just TIIPredicates). For example, this can be a first step towards implementing proper support for dependency breaking instructions in tablegen. This patch also adds a verification step on TIIPredicates in tablegen. We cannot have multiple TIIPredicates with the same name. Otherwise, this will cause build errors later on, when tablegen'd .inc files are included by cpp files and then compiled. Differential Revision: https://reviews.llvm.org/D50708 llvm-svn: 339706
57 lines
1.9 KiB
TableGen
57 lines
1.9 KiB
TableGen
//===-- X86SchedPredicates.td - X86 Scheduling Predicates --*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines scheduling predicate definitions that are common to
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// all X86 subtargets.
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//
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//===----------------------------------------------------------------------===//
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// A predicate used to identify dependency-breaking instructions that clear the
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// content of the destination register. Note that this predicate only checks if
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// input registers are the same. This predicate doesn't make any assumptions on
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// the expected instruction opcodes, because different processors may implement
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// different zero-idioms.
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def ZeroIdiomPredicate : CheckSameRegOperand<1, 2>;
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// A predicate used to check if a LEA instruction uses all three source
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// operands: base, index, and offset.
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def IsThreeOperandsLEAPredicate: CheckAll<[
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// isRegOperand(Base)
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CheckIsRegOperand<1>,
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CheckNot<CheckInvalidRegOperand<1>>,
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// isRegOperand(Index)
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CheckIsRegOperand<3>,
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CheckNot<CheckInvalidRegOperand<3>>,
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// hasLEAOffset(Offset)
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CheckAny<[
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CheckAll<[
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CheckIsImmOperand<4>,
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CheckNot<CheckZeroOperand<4>>
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]>,
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CheckNonPortable<"MI.getOperand(4).isGlobal()">
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]>
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]>;
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def LEACases : MCOpcodeSwitchCase<
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[LEA32r, LEA64r, LEA64_32r, LEA16r],
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MCReturnStatement<IsThreeOperandsLEAPredicate>
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>;
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// Used to generate the body of a TII member function.
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def IsThreeOperandsLEABody :
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MCOpcodeSwitchStatement<[LEACases], MCReturnStatement<FalsePred>>;
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// This predicate evaluates to true only if the input machine instruction is a
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// 3-operands LEA. Tablegen automatically generates a new method for it in
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// X86GenInstrInfo.
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def IsThreeOperandsLEAFn :
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TIIPredicate<"isThreeOperandsLEA", IsThreeOperandsLEABody>;
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