43e94b15ea
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
33 lines
935 B
YAML
33 lines
935 B
YAML
# RUN: llc -o - %s -mtriple=amdgcn--amdhsa -verify-machineinstrs -run-pass=greedy,virtregrewriter | FileCheck %s
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--- |
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define amdgpu_kernel void @func0() {
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ret void
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}
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...
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---
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# We should not detect any interference between v0/v1 here and only allocate
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# sgpr0-sgpr3.
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#
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# CHECK-LABEL: func0
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# CHECK: S_NOP 0, implicit-def renamable $sgpr0
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# CHECK: S_NOP 0, implicit-def renamable $sgpr3
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# CHECK: S_NOP 0, implicit-def renamable $sgpr1
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# CHECK: S_NOP 0, implicit-def renamable $sgpr2
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# CHECK: S_NOP 0, implicit renamable $sgpr0, implicit renamable $sgpr3
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# CHECK: S_NOP 0, implicit renamable $sgpr1, implicit renamable $sgpr2
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name: func0
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body: |
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bb.0:
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S_NOP 0, implicit-def undef %0.sub0 : sreg_128
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S_NOP 0, implicit-def %0.sub3
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S_NOP 0, implicit-def undef %1.sub1 : sreg_128
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S_NOP 0, implicit-def %1.sub2
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S_NOP 0, implicit %0.sub0, implicit %0.sub3
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S_NOP 0, implicit %1.sub1, implicit %1.sub2
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...
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