da8f221273
Summary: In SelectionDAG, when a store is immediately chained to another store to the same address, elide the first store as it has no observable effects. This is causes small improvements dealing with intrinsics lowered to stores. Test notes: * Many testcases overwrite store addresses multiple times and needed minor changes, mainly making stores volatile to prevent the optimization from optimizing the test away. * Many X86 test cases optimized out instructions associated with associated with va_start. * Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has dependencies to check and can probably be removed and potentially replaced with another test. Reviewers: rnk, john.brawn Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33206 llvm-svn: 303198
129 lines
4.4 KiB
LLVM
129 lines
4.4 KiB
LLVM
; RUN: llc < %s -asm-verbose=false -O3 -mtriple=armv6-apple-darwin -relocation-model=pic -mcpu=arm1136jf-s -arm-atomic-cfg-tidy=0 | FileCheck %s
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; rdar://8959122 illegal register operands for UMULL instruction
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; in cfrac nightly test.
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; Armv6 generates a umull that must write to two distinct destination regs.
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; ModuleID = 'bugpoint-reduced-simplified.bc'
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:32:64-v128:32:128-a0:0:64-n32"
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target triple = "armv6-apple-darwin10"
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define void @ptoa(i1 %tst, i8* %p8, i8 %val8) nounwind {
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entry:
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br i1 false, label %bb3, label %bb
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bb: ; preds = %entry
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br label %bb3
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bb3: ; preds = %bb, %entry
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%0 = call noalias i8* @malloc() nounwind
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br i1 %tst, label %bb46, label %bb8
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bb8: ; preds = %bb3
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%1 = getelementptr inbounds i8, i8* %0, i32 0
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store volatile i8 0, i8* %1, align 1
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%2 = call i32 @ptou() nounwind
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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%3 = udiv i32 %2, 10
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%4 = urem i32 %3, 10
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%5 = icmp ult i32 %4, 10
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%6 = trunc i32 %4 to i8
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%7 = or i8 %6, 48
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%8 = add i8 %6, 87
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%iftmp.5.0.1 = select i1 %5, i8 %7, i8 %8
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store volatile i8 %iftmp.5.0.1, i8* %p8, align 1
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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%9 = udiv i32 %2, 100
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%10 = urem i32 %9, 10
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%11 = icmp ult i32 %10, 10
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%12 = trunc i32 %10 to i8
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%13 = or i8 %12, 48
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%14 = add i8 %12, 87
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%iftmp.5.0.2 = select i1 %11, i8 %13, i8 %14
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store volatile i8 %iftmp.5.0.2, i8* %p8, align 1
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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%15 = udiv i32 %2, 10000
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%16 = urem i32 %15, 10
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%17 = icmp ult i32 %16, 10
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%18 = trunc i32 %16 to i8
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%19 = or i8 %18, 48
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%20 = add i8 %18, 87
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%iftmp.5.0.4 = select i1 %17, i8 %19, i8 %20
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store volatile i8 %iftmp.5.0.4, i8* null, align 1
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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%21 = udiv i32 %2, 100000
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%22 = urem i32 %21, 10
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%23 = icmp ult i32 %22, 10
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%iftmp.5.0.5 = select i1 %23, i8 0, i8 %val8
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store volatile i8 %iftmp.5.0.5, i8* %p8, align 1
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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%24 = udiv i32 %2, 1000000
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%25 = urem i32 %24, 10
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%26 = icmp ult i32 %25, 10
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%27 = trunc i32 %25 to i8
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%28 = or i8 %27, 48
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%29 = add i8 %27, 87
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%iftmp.5.0.6 = select i1 %26, i8 %28, i8 %29
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store volatile i8 %iftmp.5.0.6, i8* %p8, align 1
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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%30 = udiv i32 %2, 10000000
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%31 = urem i32 %30, 10
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%32 = icmp ult i32 %31, 10
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%33 = trunc i32 %31 to i8
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%34 = or i8 %33, 48
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%35 = add i8 %33, 87
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%iftmp.5.0.7 = select i1 %32, i8 %34, i8 %35
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store volatile i8 %iftmp.5.0.7, i8* %p8, align 1
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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; CHECK: umull [[REGISTER:lr|r[0-9]+]],
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; CHECK-NOT: [[REGISTER]],
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; CHECK: {{lr|r[0-9]+}}, {{lr|r[0-9]+$}}
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%36 = udiv i32 %2, 100000000
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%37 = urem i32 %36, 10
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%38 = icmp ult i32 %37, 10
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%39 = trunc i32 %37 to i8
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%40 = or i8 %39, 48
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%41 = add i8 %39, 87
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%iftmp.5.0.8 = select i1 %38, i8 %40, i8 %41
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store volatile i8 %iftmp.5.0.8, i8* null, align 1
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br label %bb46
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bb46: ; preds = %bb3
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ret void
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}
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declare noalias i8* @malloc() nounwind
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declare i32 @ptou()
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