eecb353d0e
The benchmarking summarized in http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed this is beneficial for a wide range of cores. As is to be expected, quite a few small adaptations are needed to the regressions tests, as the difference in scheduling results in: - Quite a few small instruction schedule differences. - A few changes in register allocation decisions caused by different instruction schedules. - A few changes in IfConversion decisions, due to a difference in instruction schedule and/or the estimated cost of a branch mispredict. llvm-svn: 306514
158 lines
4.4 KiB
LLVM
158 lines
4.4 KiB
LLVM
; RUN: llc -mtriple thumbv7--windows-itanium %s -o - | FileCheck %s
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@i = thread_local global i32 0
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@j = external thread_local global i32
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@k = internal thread_local global i32 0
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@l = hidden thread_local global i32 0
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@m = external hidden thread_local global i32
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@n = thread_local global i16 0
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@o = thread_local global i8 0
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define i32 @f() {
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%1 = load i32, i32* @i
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ret i32 %1
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}
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; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2
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; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44]
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; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index
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; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
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; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]]
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; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2]
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; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]]
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; CHECK-NEXT: ldr r0, {{\[}}[[TLS]], [[SLOT]]]
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; CHECK: [[CPI]]:
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; CHECK-NEXT: .long i(SECREL32)
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define i32 @e() {
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%1 = load i32, i32* @j
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ret i32 %1
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}
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; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2
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; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44]
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; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index
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; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
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; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]]
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; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2]
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; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]]
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; CHECK-NEXT: ldr r0, {{\[}}[[TLS]], [[SLOT]]]
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; CHECK: [[CPI]]:
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; CHECK-NEXT: .long j(SECREL32)
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define i32 @d() {
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%1 = load i32, i32* @k
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ret i32 %1
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}
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; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2
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; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44]
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; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index
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; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
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; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]]
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; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2]
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; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]]
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; CHECK-NEXT: ldr r0, {{\[}}[[TLS]], [[SLOT]]]
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; CHECK: [[CPI]]:
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; CHECK-NEXT: .long k(SECREL32)
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define i32 @c() {
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%1 = load i32, i32* @l
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ret i32 %1
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}
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; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2
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; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44]
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; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index
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; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
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; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]]
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; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2]
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; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]]
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; CHECK-NEXT: ldr r0, {{\[}}[[TLS]], [[SLOT]]]
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; CHECK: [[CPI]]:
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; CHECK-NEXT: .long l(SECREL32)
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define i32 @b() {
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%1 = load i32, i32* @m
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ret i32 %1
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}
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; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2
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; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44]
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; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index
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; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
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; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]]
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; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2]
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; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]]
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; CHECK-NEXT: ldr r0, {{\[}}[[TLS]], [[SLOT]]]
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; CHECK: [[CPI]]:
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; CHECK: .long m(SECREL32)
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define i16 @a() {
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%1 = load i16, i16* @n
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ret i16 %1
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}
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; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2
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; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44]
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; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index
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; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
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; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]]
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; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2]
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; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]]
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; CHECK-NEXT: ldrh r0, {{\[}}[[TLS]], [[SLOT]]]
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; CHECK: [[CPI]]:
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; CHECK: .long n(SECREL32)
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define i8 @Z() {
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%1 = load i8, i8* @o
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ret i8 %1
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}
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; CHECK: mrc p15, #0, [[TEB:r[0-9]]], c13, c0, #2
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; CHECK: ldr [[TLS_POINTER:r[0-9]]], {{\[}}[[TEB]], #44]
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; CHECK: movw [[TLS_INDEX:r[0-9]]], :lower16:_tls_index
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; CHECK-NEXT: movt [[TLS_INDEX]], :upper16:_tls_index
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; CHECK-NEXT: ldr [[INDEX:r[0-9]]], {{\[}}[[TLS_INDEX]]]
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; CHECK-NEXT: ldr{{.w}} [[TLS:r[0-9]]], {{\[}}[[TLS_POINTER]], [[INDEX]], lsl #2]
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; CHECK-NEXT: ldr [[SLOT:r[0-9]]], [[CPI:\.LCPI[0-9]+_[0-9]+]]
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; CHECK-NEXT: ldrb r0, {{\[}}[[TLS]], [[SLOT]]]
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; CHECK: [[CPI]]:
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; CHECK-NEXT: .long o(SECREL32)
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