8c4b964c5a
Enabling ARMCodeGenPrepare by default caused a whole load of
failures. This is due to zexts and truncs not being handled properly.
ZExts are messy so it's just easier to disable for now and truncs
are allowed only as 'sinks'. I still need to figure out why allowing
them as 'sources' causes so many failures. The other main changes are
that we are explicit in the types that we converting to, it's now
always 'TypeSize'. Type support is also now performed while checking
for valid opcodes as it unnecessarily complicated having the checks
are different stages.
I've moved the tests around too, so we have the zext and truncs in
their own file as well as the overflowing opcode tests.
Differential Revision: https://reviews.llvm.org/D50518
llvm-svn: 339432
50 lines
1.2 KiB
LLVM
50 lines
1.2 KiB
LLVM
; RUN: llc -mtriple=thumbv8.main -mcpu=cortex-m33 %s -arm-disable-cgp=false -o - | FileCheck %s
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; CHECK: overflow_add
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; CHECK: add
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; CHECK: uxth
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; CHECK: cmp
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define zeroext i16 @overflow_add(i16 zeroext %a, i16 zeroext %b) {
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%add = add i16 %a, %b
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%or = or i16 %add, 1
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%cmp = icmp ugt i16 %or, 1024
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%res = select i1 %cmp, i16 2, i16 5
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ret i16 %res
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}
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; CHECK-LABEL: overflow_sub
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; CHECK: sub
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; CHECK: uxth
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; CHECK: cmp
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define zeroext i16 @overflow_sub(i16 zeroext %a, i16 zeroext %b) {
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%add = sub i16 %a, %b
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%or = or i16 %add, 1
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%cmp = icmp ugt i16 %or, 1024
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%res = select i1 %cmp, i16 2, i16 5
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ret i16 %res
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}
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; CHECK-LABEL: overflow_mul
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; CHECK: mul
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; CHECK: uxth
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; CHECK: cmp
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define zeroext i16 @overflow_mul(i16 zeroext %a, i16 zeroext %b) {
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%add = mul i16 %a, %b
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%or = or i16 %add, 1
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%cmp = icmp ugt i16 %or, 1024
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%res = select i1 %cmp, i16 2, i16 5
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ret i16 %res
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}
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; CHECK-LABEL: overflow_shl
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; CHECK-COMMON: lsl
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; CHECK-COMMON: uxth
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; CHECK-COMMON: cmp
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define zeroext i16 @overflow_shl(i16 zeroext %a, i16 zeroext %b) {
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%add = shl i16 %a, %b
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%or = or i16 %add, 1
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%cmp = icmp ugt i16 %or, 1024
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%res = select i1 %cmp, i16 2, i16 5
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ret i16 %res
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}
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