b32ff46ff7
Disable ARMCodeGenPrepare by default again. It is causing verifier
failues in V8 that look like:
Duplicate integer as switch case
switch i32 %trunc, label %if.end13 [
i32 0, label %cleanup36
i32 0, label %if.then8
], !dbg !4981
i32 0
fatal error: error in backend: Broken function found, compilation aborted!
I will continue reducing the test case and send it along.
llvm-svn: 338452
46 lines
1.2 KiB
LLVM
46 lines
1.2 KiB
LLVM
; RUN: llc -mtriple=thumbv7m -arm-disable-cgp=false %s -o - | FileCheck %s
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; RUN: llc -mtriple=thumbv8m.main -arm-disable-cgp=false %s -o - | FileCheck %s
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; RUN: llc -mtriple=thumbv7 %s -arm-disable-cgp=false -o - | FileCheck %s
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; RUN: llc -mtriple=armv8 %s -arm-disable-cgp=false -o - | FileCheck %s
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; Test to check that ARMCodeGenPrepare doesn't optimised away sign extends.
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; CHECK-LABEL: test_signed_load:
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; CHECK: uxth
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define i16 @test_signed_load(i16* %ptr) {
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%load = load i16, i16* %ptr
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%conv0 = zext i16 %load to i32
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%conv1 = sext i16 %load to i32
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%cmp = icmp eq i32 %conv0, %conv1
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%conv2 = zext i1 %cmp to i16
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ret i16 %conv2
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}
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; Don't allow sign bit generating opcodes.
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; CHECK-LABEL: test_ashr:
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; CHECK: sxth
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define i16 @test_ashr(i16 zeroext %arg) {
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%ashr = ashr i16 %arg, 1
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%cmp = icmp eq i16 %ashr, 0
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%conv = zext i1 %cmp to i16
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ret i16 %conv
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}
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; CHECK-LABEL: test_sdiv:
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; CHECK: sxth
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define i16 @test_sdiv(i16 zeroext %arg) {
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%sdiv = sdiv i16 %arg, 2
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%cmp = icmp ne i16 %sdiv, 0
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%conv = zext i1 %cmp to i16
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ret i16 %conv
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}
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; CHECK-LABEL: test_srem
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; CHECK: sxth
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define i16 @test_srem(i16 zeroext %arg) {
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%srem = srem i16 %arg, 4
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%cmp = icmp ne i16 %srem, 0
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%conv = zext i1 %cmp to i16
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ret i16 %conv
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}
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