d2c739230c
The original code attempted to do this, but the std::abs() call didn't actually do anything due to implicit type conversions. Fix the type conversions, and perform the correct check for negative immediates. This probably has very little practical impact, but it's worth fixing just to avoid confusion in the future, I think. Differential Revision: https://reviews.llvm.org/D48907 llvm-svn: 336742
147 lines
6.2 KiB
LLVM
147 lines
6.2 KiB
LLVM
; RUN: llc %s -o - -enable-shrink-wrap=true | FileCheck %s --check-prefix=CHECK --check-prefix=ENABLE
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; RUN: llc %s -o - -enable-shrink-wrap=false | FileCheck %s --check-prefix=CHECK --check-prefix=DISABLE
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; We cannot merge this test with the main test for shrink-wrapping, because
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; the code path we want to exerce is not taken with ios lowering.
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n8:16:32-S64"
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target triple = "armv7--linux-gnueabi"
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@skip = internal unnamed_addr constant [2 x i8] c"\01\01", align 1
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; Check that we do not restore the before having used the saved CSRs.
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; This happened because of a bad use of the post-dominance property.
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; The exit block of the loop happens to also lead to defs/uses of CSRs.
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; It also post-dominates the loop body and we use to generate invalid
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; restore sequence. I.e., we restored too early.
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;
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; CHECK-LABEL: wrongUseOfPostDominate:
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;
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; The prologue is the first thing happening in the function
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; without shrink-wrapping.
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; DISABLE: push
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;
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; CHECK: cmn r1, #1
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;
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; With shrink-wrapping, we branch to a pre-header, where the prologue
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; is located.
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; ENABLE-NEXT: ble [[LOOP_PREHEADER:[.a-zA-Z0-9_]+]]
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; Without shrink-wrapping, we go straight into the loop.
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; DISABLE-NEXT: ble [[LOOP_HEADER:[.a-zA-Z0-9_]+]]
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;
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; CHECK: @ %if.end29
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; DISABLE-NEXT: pop
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; ENABLE-NEXT: bx lr
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;
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; ENABLE: [[LOOP_PREHEADER]]
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; ENABLE: push
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; We must not find a pop here, otherwise that means we are in the loop
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; and are restoring before using the saved CSRs.
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; ENABLE-NOT: pop
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; ENALBE-NEXT: [[LOOP_HEADER:[.a-zA-Z0-9_]+]]: @ %while.cond2.outer
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;
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; DISABLE: [[LOOP_HEADER]]: @ %while.cond2.outer
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;
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; ENABLE-NOT: pop
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;
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; CHECK: @ %while.cond2
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; CHECK: add
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; CHECK-NEXT: cmp r{{[0-1]+}}, #1
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; Jump to the return block
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; CHECK-NEXT: beq [[RETURN_BLOCK:[.a-zA-Z0-9_]+]]
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;
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; Use the back edge to check we get the label of the loop right.
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; This is to make sure we check the right loop pattern.
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; CHECK: @ %while.body24.land.rhs14_crit_edge
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; CHECK: cmp r{{[0-9]+}}, #192
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; CHECK-NEXT bhs [[LOOP_HEADER]]
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;
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; CHECK: [[RETURN_BLOCK]]:
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; Set the return value.
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; CHECK-NEXT: mov r0,
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; CHECK-NEXT: pop
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define fastcc i8* @wrongUseOfPostDominate(i8* readonly %s, i32 %off, i8* readnone %lim) {
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entry:
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%cmp = icmp sgt i32 %off, -1
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br i1 %cmp, label %while.cond.preheader, label %while.cond2.outer
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while.cond.preheader: ; preds = %entry
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%tobool4 = icmp ne i32 %off, 0
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%cmp15 = icmp ult i8* %s, %lim
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%sel66 = and i1 %tobool4, %cmp15
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br i1 %sel66, label %while.body, label %if.end29
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while.body: ; preds = %while.body, %while.cond.preheader
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%s.addr.08 = phi i8* [ %add.ptr, %while.body ], [ %s, %while.cond.preheader ]
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%off.addr.07 = phi i32 [ %dec, %while.body ], [ %off, %while.cond.preheader ]
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%dec = add nsw i32 %off.addr.07, -1
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%tmp = load i8, i8* %s.addr.08, align 1, !tbaa !2
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%idxprom = zext i8 %tmp to i32
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%arrayidx = getelementptr inbounds [2 x i8], [2 x i8]* @skip, i32 0, i32 %idxprom
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%tmp1 = load i8, i8* %arrayidx, align 1, !tbaa !2
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%conv = zext i8 %tmp1 to i32
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%add.ptr = getelementptr inbounds i8, i8* %s.addr.08, i32 %conv
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%tobool = icmp ne i32 %off.addr.07, 1
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%cmp1 = icmp ult i8* %add.ptr, %lim
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%sel6 = and i1 %tobool, %cmp1
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br i1 %sel6, label %while.body, label %if.end29
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while.cond2.outer: ; preds = %while.body24.land.rhs14_crit_edge, %while.body24, %land.rhs14.preheader, %if.then7, %entry
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%off.addr.1.ph = phi i32 [ %off, %entry ], [ %inc, %land.rhs14.preheader ], [ %inc, %if.then7 ], [ %inc, %while.body24.land.rhs14_crit_edge ], [ %inc, %while.body24 ]
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%s.addr.1.ph = phi i8* [ %s, %entry ], [ %incdec.ptr, %land.rhs14.preheader ], [ %incdec.ptr, %if.then7 ], [ %lsr.iv, %while.body24.land.rhs14_crit_edge ], [ %lsr.iv, %while.body24 ]
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br label %while.cond2
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while.cond2: ; preds = %while.body4, %while.cond2.outer
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%off.addr.1 = phi i32 [ %inc, %while.body4 ], [ %off.addr.1.ph, %while.cond2.outer ]
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%inc = add nsw i32 %off.addr.1, 1
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%tobool3 = icmp eq i32 %off.addr.1, 0
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br i1 %tobool3, label %if.end29, label %while.body4
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while.body4: ; preds = %while.cond2
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%tmp2 = icmp ugt i8* %s.addr.1.ph, %lim
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br i1 %tmp2, label %if.then7, label %while.cond2
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if.then7: ; preds = %while.body4
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%incdec.ptr = getelementptr inbounds i8, i8* %s.addr.1.ph, i32 -1
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%tmp3 = load i8, i8* %incdec.ptr, align 1, !tbaa !2
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%conv1525 = zext i8 %tmp3 to i32
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%tobool9 = icmp slt i8 %tmp3, 0
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%cmp129 = icmp ugt i8* %incdec.ptr, %lim
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%or.cond13 = and i1 %tobool9, %cmp129
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br i1 %or.cond13, label %land.rhs14.preheader, label %while.cond2.outer
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land.rhs14.preheader: ; preds = %if.then7
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%cmp1624 = icmp slt i8 %tmp3, 0
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%cmp2026 = icmp ult i32 %conv1525, 192
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%or.cond27 = and i1 %cmp1624, %cmp2026
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br i1 %or.cond27, label %while.body24.preheader, label %while.cond2.outer
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while.body24.preheader: ; preds = %land.rhs14.preheader
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%scevgep = getelementptr i8, i8* %s.addr.1.ph, i32 -2
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br label %while.body24
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while.body24: ; preds = %while.body24.land.rhs14_crit_edge, %while.body24.preheader
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%lsr.iv = phi i8* [ %scevgep, %while.body24.preheader ], [ %scevgep34, %while.body24.land.rhs14_crit_edge ]
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%cmp12 = icmp ugt i8* %lsr.iv, %lim
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br i1 %cmp12, label %while.body24.land.rhs14_crit_edge, label %while.cond2.outer
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while.body24.land.rhs14_crit_edge: ; preds = %while.body24
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%.pre = load i8, i8* %lsr.iv, align 1, !tbaa !2
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%cmp16 = icmp slt i8 %.pre, 0
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%conv15 = zext i8 %.pre to i32
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%cmp20 = icmp ult i32 %conv15, 192
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%or.cond = and i1 %cmp16, %cmp20
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%scevgep34 = getelementptr i8, i8* %lsr.iv, i32 -1
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br i1 %or.cond, label %while.body24, label %while.cond2.outer
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if.end29: ; preds = %while.cond2, %while.body, %while.cond.preheader
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%s.addr.3 = phi i8* [ %s, %while.cond.preheader ], [ %add.ptr, %while.body ], [ %s.addr.1.ph, %while.cond2 ]
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ret i8* %s.addr.3
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}
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!llvm.module.flags = !{!0, !1}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 1, !"min_enum_size", i32 4}
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!2 = !{!3, !3, i64 0}
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!3 = !{!"omnipotent char", !4, i64 0}
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!4 = !{!"Simple C/C++ TBAA"}
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