d91a9e27a9
This will remove suboptimal branching from the generated ll/sc loops. The extra simplification pass affects a lot of testcases, which have been modified to accommodate this change: either by modifying the test to become immune to the CFG simplification, or (less preferablt) by adding option -hexagon-initial-cfg-clenaup=0. llvm-svn: 338774
30 lines
1.0 KiB
LLVM
30 lines
1.0 KiB
LLVM
; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s
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; Make sure we can select QFALSE.
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; CHECK: vcmp.gt(v0.w,v0.w)
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target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
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target triple = "hexagon"
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; Function Attrs: nounwind
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define hidden fastcc void @fred(i32 %a0) #0 {
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b1:
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%v2 = insertelement <32 x i32> undef, i32 %a0, i32 0
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%v3 = shufflevector <32 x i32> %v2, <32 x i32> undef, <32 x i32> zeroinitializer
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%v4 = icmp eq <32 x i32> %v3, undef
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%v5 = and <32 x i1> zeroinitializer, %v4
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br label %b6
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b6: ; preds = %b1
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%v7 = extractelement <32 x i1> %v5, i32 22
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br i1 %v7, label %b8, label %b9
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b8: ; preds = %b6
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unreachable
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b9: ; preds = %b6
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unreachable
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
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