e1983bcf55
This patch lets the llvm tools handle the new HVX target features that
are added by frontend (clang). The target-features are of the form
"hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX.
"hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated.
The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}.
Eg: "+hvxv62"
For the correct HVX code generation, the user must use the following
target features.
For 64B mode: "+hvxv62" "+hvx-length64b"
For 128B mode: "+hvxv62" "+hvx-length128b"
Clang picks a default length if none is specified. If for some reason,
no hvx-length is specified to llvm, the compilation will bail out.
There is a corresponding clang patch.
Differential Revision: https://reviews.llvm.org/D38851
llvm-svn: 316101
72 lines
2.0 KiB
LLVM
72 lines
2.0 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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target triple = "hexagon"
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; CHECK-LABEL: dc00:
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; CHECK: dcfetch
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define void @dc00(i8* nocapture readonly %p) local_unnamed_addr #0 {
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tail call void @llvm.hexagon.prefetch(i8* %p)
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ret void
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}
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; CHECK-LABEL: dc01:
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; CHECK: dccleana
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define void @dc01(i8* nocapture readonly %p) local_unnamed_addr #0 {
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entry:
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tail call void @llvm.hexagon.Y2.dccleana(i8* %p)
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ret void
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}
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; CHECK-LABEL: dc02:
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; CHECK: dccleaninva
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define void @dc02(i8* nocapture readonly %p) local_unnamed_addr #0 {
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entry:
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tail call void @llvm.hexagon.Y2.dccleaninva(i8* %p)
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ret void
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}
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; CHECK-LABEL: dc03:
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; CHECK: dcinva
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define void @dc03(i8* nocapture readonly %p) local_unnamed_addr #0 {
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entry:
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tail call void @llvm.hexagon.Y2.dcinva(i8* %p)
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ret void
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}
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; CHECK-LABEL: dc04:
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; CHECK: dczeroa
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define void @dc04(i8* nocapture %p) local_unnamed_addr #0 {
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entry:
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tail call void @llvm.hexagon.Y2.dczeroa(i8* %p)
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ret void
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}
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; CHECK-LABEL: dc05:
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; CHECK: l2fetch(r{{[0-9]+}},r{{[0-9]+}})
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define void @dc05(i8* nocapture readonly %p, i32 %q) local_unnamed_addr #0 {
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entry:
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tail call void @llvm.hexagon.Y4.l2fetch(i8* %p, i32 %q)
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ret void
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}
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; CHECK-LABEL: dc06:
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; CHECK: l2fetch(r{{[0-9]+}},r{{[0-9]+}}:{{[0-9]+}})
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define void @dc06(i8* nocapture readonly %p, i64 %q) local_unnamed_addr #0 {
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entry:
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tail call void @llvm.hexagon.Y5.l2fetch(i8* %p, i64 %q)
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ret void
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}
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declare void @llvm.hexagon.prefetch(i8* nocapture) #1
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declare void @llvm.hexagon.Y2.dccleana(i8* nocapture readonly) #2
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declare void @llvm.hexagon.Y2.dccleaninva(i8* nocapture readonly) #2
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declare void @llvm.hexagon.Y2.dcinva(i8* nocapture readonly) #2
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declare void @llvm.hexagon.Y2.dczeroa(i8* nocapture) #3
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declare void @llvm.hexagon.Y4.l2fetch(i8* nocapture readonly, i32) #2
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declare void @llvm.hexagon.Y5.l2fetch(i8* nocapture readonly, i64) #2
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="-hvx,-long-calls" }
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attributes #1 = { inaccessiblemem_or_argmemonly nounwind }
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attributes #2 = { nounwind }
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attributes #3 = { argmemonly nounwind writeonly }
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