d5a00b0ff6
This should enable us to test the generation of target-specific constant pools, e.g. for ARM: constants: - id: 0 value: 'g(GOT_PREL)-(LPC0+8-.)' alignment: 4 isTargetSpecific: true I intend to use this to test PIC support in GlobalISel for ARM. This is difficult to test outside of that context, since the existing MIR tests usually rely on parser support as well, and that seems a bit trickier to add. We could try to add a unit test, but the setup for that seems rather convoluted and overkill. We do test however that the parser reports a nice error when encountering a target-specific constant pool. Differential Revision: https://reviews.llvm.org/D36092 llvm-svn: 309806
28 lines
851 B
YAML
28 lines
851 B
YAML
# RUN: not llc -mtriple arm-unknown -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
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--- |
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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@g = private global i32 4
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define void @target_constant_pool() { ret void }
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...
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---
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name: target_constant_pool
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gpr, preferred-register: '' }
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- { id: 1, class: gpr, preferred-register: '' }
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constants:
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- id: 0
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# CHECK: [[@LINE+1]]:22: Can't parse target-specific constant pool entries yet
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value: 'g-(LPC0+8)'
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alignment: 4
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isTargetSpecific: true
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body: |
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bb.0.entry:
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%0 = LDRi12 %const.0, 0, 14, _ :: (load 4 from constant-pool)
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%1 = PICLDR killed %0, 0, 14, _ :: (dereferenceable load 4 from @g)
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%r0 = COPY %1
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BX_RET 14, _, implicit %r0
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...
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