3af2c992dc
This change fixes the issue that arises when we duplicate condition from the predecessor block. If the condition's arguments are not considered alive across the blocks, fast regalloc gets confused and starts generating reloads from the slots that have never been spilled to. This change also leads to smaller code given that, unlike on architectures with condition codes, on Mips we can branch directly on register value, thus we gain nothing by duplication. Patch by Dragan Mladjenovic. Differential Revision: https://reviews.llvm.org/D48642 llvm-svn: 336084
29 lines
890 B
LLVM
29 lines
890 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=mipsel -relocation-model=pic -O0 -fast-isel=true -mcpu=mips32r2 \
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; RUN: < %s -verify-machineinstrs | FileCheck %s
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define i32 @foobar(i32*) {
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bb0:
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; CHECK-LABEL: foobar:
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; CHECK: # %bb.0: # %bb0
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; CHECK: lw $[[REG0:[0-9]+]], 0($4)
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; CHECK-NEXT: sltiu $[[REG1:[0-9]+]], $[[REG0]], 1
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; CHECK: sw $[[REG1]], [[SPILL:[0-9]+]]($sp) # 4-byte Folded Spill
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%1 = load i32, i32* %0 , align 4
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%2 = icmp eq i32 %1, 0
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store atomic i32 0, i32* %0 monotonic, align 4
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br label %bb1
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bb1:
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; CHECK: # %bb.1: # %bb1
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; CHECK-NEXT: lw $[[REG2:[0-9]+]], [[SPILL]]($sp) # 4-byte Folded Reload
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; CHECK-NEXT: bgtz $[[REG2]], $BB0_3
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br i1 %2, label %bb2, label %bb3
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bb2:
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; CHECK: $BB0_3: # %bb2
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; CHECK-NEXT: addiu $2, $zero, 1
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ret i32 1
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bb3:
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ret i32 0
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}
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