54e22f33d9
Recommiting with compiler time improvements
Recommitting after fixup of 32-bit aliasing sign offset bug in DAGCombiner.
* Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search and chain alias analysis which only
checks for parallel stores through the chain subgraph. This is cleaner
as the separation of non-interfering loads/stores from the
store-merging logic.
When merging stores search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited.
This improves the quality of the output SelectionDAG and the output
Codegen (save perhaps for some ARM cases where we correctly constructs
wider loads, but then promotes them to float operations which appear
but requires more expensive constant generation).
Some minor peephole optimizations to deal with improved SubDAG shapes (listed below)
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the chain aggregation in the merged stores across code
paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seems sufficient to not cause regressions in
tests.
5. Remove Chain dependencies of Memory operations on CopyfromReg
nodes as these are captured by data dependence
6. Forward loads-store values through tokenfactors containing
{CopyToReg,CopyFromReg} Values.
7. Peephole to convert buildvector of extract_vector_elt to
extract_subvector if possible (see
CodeGen/AArch64/store-merge.ll)
8. Store merging for the ARM target is restricted to 32-bit as
some in some contexts invalid 64-bit operations are being
generated. This can be removed once appropriate checks are
added.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable, improving load-store forwarding. One test in
particular is worth noting:
CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store
forwarding converts a load-store pair into a parallel store and
a memory-realized bitcast of the same value. However, because we
lose the sharing of the explicit and implicit store values we
must create another local store. A similar transformation
happens before SelectionDAG as well.
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle
llvm-svn: 297695
224 lines
10 KiB
LLVM
224 lines
10 KiB
LLVM
; RUN: llc -march=mips -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefixes=ALL,SYM32,O32,O32BE %s
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; RUN: llc -march=mipsel -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefixes=ALL,SYM32,O32,O32LE %s
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; RUN-TODO: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s
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; RUN-TODO: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s
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; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s
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; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s
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; RUN: llc -march=mips64 -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW %s
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; RUN: llc -march=mips64el -relocation-model=static -mattr=+soft-float -target-abi n64 < %s | FileCheck --check-prefixes=ALL,SYM64,NEW %s
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; Test the floating point arguments for all ABI's and byte orders as specified
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; by section 5 of MD00305 (MIPS ABIs Described).
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;
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; N32/N64 are identical in this area so their checks have been combined into
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; the 'NEW' prefix (the N stands for New).
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@bytes = global [11 x i8] zeroinitializer
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@dwords = global [11 x i64] zeroinitializer
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@floats = global [11 x float] zeroinitializer
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@doubles = global [11 x double] zeroinitializer
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define void @double_args(double %a, double %b, double %c, double %d, double %e,
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double %f, double %g, double %h, double %i) nounwind {
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entry:
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%0 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 1
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store volatile double %a, double* %0
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%1 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 2
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store volatile double %b, double* %1
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%2 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 3
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store volatile double %c, double* %2
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%3 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 4
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store volatile double %d, double* %3
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%4 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 5
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store volatile double %e, double* %4
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%5 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 6
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store volatile double %f, double* %5
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%6 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 7
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store volatile double %g, double* %6
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%7 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 8
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store volatile double %h, double* %7
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%8 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 9
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store volatile double %i, double* %8
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ret void
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}
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; ALL-LABEL: double_args:
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; We won't test the way the global address is calculated in this test. This is
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; just to get the register number for the other checks.
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; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles)
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; SYM64-DAG: daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(doubles)
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; The first four arguments are the same in O32/N32/N64.
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; The first argument is floating point but soft-float is enabled so floating
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; point registers are not used.
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; O32-DAG: sw $4, 8([[R2]])
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; O32-DAG: sw $5, 12([[R2]])
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; NEW-DAG: sd $4, 8([[R2]])
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; O32-DAG: sw $6, 16([[R2]])
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; O32-DAG: sw $7, 20([[R2]])
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; NEW-DAG: sd $5, 16([[R2]])
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; O32 has run out of argument registers and starts using the stack
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; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 16($sp)
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; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 20($sp)
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; O32-DAG: sw [[R3]], 24([[R2]])
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; O32-DAG: sw [[R4]], 28([[R2]])
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; NEW-DAG: sd $6, 24([[R2]])
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; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 24($sp)
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; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 28($sp)
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; O32-DAG: sw [[R3]], 32([[R2]])
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; O32-DAG: sw [[R4]], 36([[R2]])
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; NEW-DAG: sd $7, 32([[R2]])
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; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 32($sp)
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; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 36($sp)
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; O32-DAG: sw [[R3]], 40([[R2]])
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; O32-DAG: sw [[R4]], 44([[R2]])
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; NEW-DAG: sd $8, 40([[R2]])
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; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 40($sp)
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; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 44($sp)
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; O32-DAG: sw [[R3]], 48([[R2]])
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; O32-DAG: sw [[R4]], 52([[R2]])
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; NEW-DAG: sd $9, 48([[R2]])
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; O32-DAG: lw [[R3:\$([0-9]+|gp)]], 48($sp)
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; O32-DAG: lw [[R4:\$([0-9]+|gp)]], 52($sp)
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; O32-DAG: sw [[R3]], 56([[R2]])
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; O32-DAG: sw [[R4]], 60([[R2]])
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; NEW-DAG: sd $10, 56([[R2]])
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; N32/N64 have run out of registers and starts using the stack too
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; O32-DAG: lw [[R3:\$[0-9]+]], 56($sp)
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; O32-DAG: lw [[R4:\$[0-9]+]], 60($sp)
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; O32-DAG: sw [[R3]], 64([[R2]])
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; O32-DAG: sw [[R4]], 68([[R2]])
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; NEW-DAG: ld [[R3:\$[0-9]+]], 0($sp)
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; NEW-DAG: sd $11, 64([[R2]])
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define void @float_args(float %a, float %b, float %c, float %d, float %e,
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float %f, float %g, float %h, float %i, float %j)
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nounwind {
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entry:
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%0 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 1
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store volatile float %a, float* %0
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%1 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 2
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store volatile float %b, float* %1
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%2 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 3
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store volatile float %c, float* %2
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%3 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 4
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store volatile float %d, float* %3
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%4 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 5
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store volatile float %e, float* %4
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%5 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 6
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store volatile float %f, float* %5
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%6 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 7
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store volatile float %g, float* %6
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%7 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 8
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store volatile float %h, float* %7
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%8 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 9
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store volatile float %i, float* %8
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%9 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 10
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store volatile float %j, float* %9
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ret void
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}
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; ALL-LABEL: float_args:
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; We won't test the way the global address is calculated in this test. This is
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; just to get the register number for the other checks.
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; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(floats)
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; SYM64-DAG: daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(floats)
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; The first four arguments are the same in O32/N32/N64.
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; The first argument is floating point but soft-float is enabled so floating
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; point registers are not used.
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; MD00305 and GCC disagree on this one. MD00305 says that floats are treated
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; as 8-byte aligned and occupy two slots on O32. GCC is treating them as 4-byte
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; aligned and occupying one slot. We'll use GCC's definition.
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; ALL-DAG: sw $4, 4([[R2]])
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; ALL-DAG: sw $5, 8([[R2]])
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; ALL-DAG: sw $6, 12([[R2]])
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; ALL-DAG: sw $7, 16([[R2]])
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; O32 has run out of argument registers and starts using the stack
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; O32-DAG: lw [[R3:\$[0-9]+]], 16($sp)
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; O32-DAG: sw [[R3]], 20([[R2]])
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; NEW-DAG: sw $8, 20([[R2]])
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; O32-DAG: lw [[R3:\$[0-9]+]], 20($sp)
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; O32-DAG: sw [[R3]], 24([[R2]])
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; NEW-DAG: sw $9, 24([[R2]])
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; O32-DAG: lw [[R3:\$[0-9]+]], 24($sp)
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; O32-DAG: sw [[R3]], 28([[R2]])
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; NEW-DAG: sw $10, 28([[R2]])
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; O32-DAG: lw [[R3:\$[0-9]+]], 28($sp)
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; O32-DAG: sw [[R3]], 32([[R2]])
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; NEW-DAG: sw $11, 32([[R2]])
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; N32/N64 have run out of registers and start using the stack too
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; O32-DAG: lw [[R3:\$[0-9]+]], 32($sp)
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; O32-DAG: sw [[R3]], 36([[R2]])
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; NEW-DAG: lw [[R3:\$[0-9]+]], 0($sp)
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; NEW-DAG: sw [[R3]], 36([[R2]])
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define void @double_arg2(i8 %a, double %b) nounwind {
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entry:
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%0 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 1
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store volatile i8 %a, i8* %0
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%1 = getelementptr [11 x double], [11 x double]* @doubles, i32 0, i32 1
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store volatile double %b, double* %1
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ret void
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}
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; ALL-LABEL: double_arg2:
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; We won't test the way the global address is calculated in this test. This is
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; just to get the register number for the other checks.
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; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
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; SYM64-DAG: daddiu [[R1:\$[0-9]]], ${{[0-9]+}}, %lo(bytes)
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; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(doubles)
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; SYM64-DAG: daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(doubles)
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; The first four arguments are the same in O32/N32/N64.
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; The first argument isn't floating point so floating point registers are not
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; used.
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; The second slot is insufficiently aligned for double on O32 so it is skipped.
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; Also, double occupies two slots on O32 and only one for N32/N64.
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; ALL-DAG: sb $4, 1([[R1]])
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; O32-DAG: sw $6, 8([[R2]])
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; O32-DAG: sw $7, 12([[R2]])
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; NEW-DAG: sd $5, 8([[R2]])
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define void @float_arg2(i8 signext %a, float %b) nounwind {
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entry:
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%0 = getelementptr [11 x i8], [11 x i8]* @bytes, i32 0, i32 1
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store volatile i8 %a, i8* %0
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%1 = getelementptr [11 x float], [11 x float]* @floats, i32 0, i32 1
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store volatile float %b, float* %1
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ret void
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}
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; ALL-LABEL: float_arg2:
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; We won't test the way the global address is calculated in this test. This is
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; just to get the register number for the other checks.
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; SYM32-DAG: addiu [[R1:\$[0-9]+]], ${{[0-9]+}}, %lo(bytes)
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; SYM64-DAG: daddiu [[R1:\$[0-9]]], ${{[0-9]+}}, %lo(bytes)
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; SYM32-DAG: addiu [[R2:\$[0-9]+]], ${{[0-9]+}}, %lo(floats)
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; SYM64-DAG: daddiu [[R2:\$[0-9]]], ${{[0-9]+}}, %lo(floats)
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; The first four arguments are the same in O32/N32/N64.
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; The first argument isn't floating point so floating point registers are not
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; used.
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; MD00305 and GCC disagree on this one. MD00305 says that floats are treated
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; as 8-byte aligned and occupy two slots on O32. GCC is treating them as 4-byte
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; aligned and occupying one slot. We'll use GCC's definition.
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; ALL-DAG: sb $4, 1([[R1]])
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; ALL-DAG: sw $5, 4([[R2]])
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