b3e7ed3b94
Instructions affected: mthc1, mfhc1, add.d, sub.d, mul.d, div.d, mov.d, neg.d, cvt.w.d, cvt.d.s, cvt.d.w, cvt.s.d These instructions are now defined for microMIPS32r3 + microMIPS32r6 in MicroMipsInstrFPU.td since they shared their encoding with those already defined in microMIPS32r6InstrInfo.td and have been therefore removed from the latter file. Some instructions present in MicroMipsInstrFPU.td which did not have both AFGR64 and FGR64 variants defined have been altered to do so. Differential revision: https://reviews.llvm.org/D42738 llvm-svn: 324584
31 lines
1.6 KiB
LLVM
31 lines
1.6 KiB
LLVM
; RUN: llc -march=mips -mcpu=mips32r2 -asm-show-inst \
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; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MIPS32R2
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; RUN: llc -march=mips -mcpu=mips32r2 -mattr=+fp64 -asm-show-inst \
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; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MIPS32FP64
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; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips -asm-show-inst \
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; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MM
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; RUN: llc -march=mips -mcpu=mips32r3 -mattr=+micromips,+fp64 -asm-show-inst \
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; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MMFP64
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; RUN: llc -march=mips -mcpu=mips32r6 -mattr=+micromips -asm-show-inst \
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; RUN: -mno-ldc1-sdc1 < %s | FileCheck %s --check-prefix=MMR6
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define double @mthc1(i64 %a) {
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; MIPS32R2: mthc1 {{.*}} # <MCInst #{{[0-9]+}} MTHC1_D32
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; MIPS32FP64: mthc1 {{.*}} # <MCInst #{{[0-9]+}} MTHC1_D64
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; MM: mthc1 {{.*}} # <MCInst #{{[0-9]+}} MTHC1_D32_MM
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; MMFP64: mthc1 {{.*}} # <MCInst #{{[0-9]+}} MTHC1_D64_MM
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; MMR6: mthc1 {{.*}} # <MCInst #{{[0-9]+}} MTHC1_D64_MM
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%1 = bitcast i64 %a to double
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ret double %1
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}
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define i64 @mfhc1(double %a) {
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; MIPS32R2: mfhc1 {{.*}} # <MCInst #{{[0-9]+}} MFHC1_D32
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; MIPS32FP64: mfhc1 {{.*}} # <MCInst #{{[0-9]+}} MFHC1_D64
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; MM: mfhc1 {{.*}} # <MCInst #{{[0-9]+}} MFHC1_D32_MM
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; MMFP64: mfhc1 {{.*}} # <MCInst #{{[0-9]+}} MFHC1_D64_MM
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; MMR6: mfhc1 {{.*}} # <MCInst #{{[0-9]+}} MFHC1_D64_MM
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%1 = bitcast double %a to i64
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ret i64 %1
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}
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