b2368fbdf4
This seems to improve X86's ability to match this into an address computation. Otherwise the other operand gets assigned to the base register and the stack pointer + frame index ends up in the index register. But index registers can't encode ESP/RSP so we end up having to move it into another register to meet the constraint. I could try to improve the address matcher in X86, but swapping the producer seemed easier. Several other places already have the operands in this order so this is at least consistent. llvm-svn: 321370
20 lines
838 B
LLVM
20 lines
838 B
LLVM
; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s -check-prefix=ALL
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; This test triggered a bug in the vector splitting where the type legalizer
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; attempted to extract the element with by storing the vector, then reading
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; an element back. However, the address calculation was:
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; Base + Index * (EltSizeInBits / 8)
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; and EltSizeInBits was 1. This caused the index to be forgotten.
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define i1 @via_stack_bug(i8 signext %idx) {
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%1 = extractelement <2 x i1> <i1 false, i1 true>, i8 %idx
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ret i1 %1
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}
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; ALL-LABEL: via_stack_bug:
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; ALL-DAG: addiu [[ONE:\$[0-9]+]], $zero, 1
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; ALL-DAG: sh [[ONE]], 6($sp)
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; ALL-DAG: andi [[MASKED_IDX:\$[0-9]+]], $4, 1
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; ALL-DAG: addiu [[VPTR:\$[0-9]+]], $sp, 6
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; ALL-DAG: or [[EPTR:\$[0-9]+]], [[VPTR]], [[MASKED_IDX]]
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; ALL: lbu $2, 0([[EPTR]])
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