6ccbd16433
Add patterns for unhandled CondCode enumerables: SETEQ, SETGE, SETGT, SETLE, SETLT, SETNE. Stated at the ISD::CondCode enum declaration: `All of these (except for the 'always folded ops') should be handled for floating point.` Add patterns which use these nodes, same as corresponding 'ordered' CondCode nodes. Referring to 'Ordered means that neither operand is a QNAN' we assume it is safe to match ex. SETLT node to the same instruction as SETOLT. Differential Revision: https://reviews.llvm.org/D50757 llvm-svn: 340392
64 lines
1.5 KiB
LLVM
64 lines
1.5 KiB
LLVM
; RUN: llc -mtriple mips64-unknown-linux -mcpu=mips64r5 -mattr=+msa < %s | FileCheck %s
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; The fcmp fast flag will result in conversion from
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; setolt, setoeq, setole, setone to
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; setlt, seteq, setle, setne nodes.
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; Test that the latter nodes are matched to the same instructions as the former.
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define <2 x i1> @testlt_v2f64(<2 x double> %a, <2 x double> %b) {
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start:
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%0 = fcmp fast olt <2 x double> %a, %b
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; CHECK: fclt.d
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ret <2 x i1> %0
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}
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define <4 x i1> @testlt_v4f32(<4 x float> %a, <4 x float> %b) {
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start:
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%0 = fcmp fast olt <4 x float> %a, %b
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; CHECK: fclt.w
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ret <4 x i1> %0
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}
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define <2 x i1> @testeq_v2f64(<2 x double> %a, <2 x double> %b) {
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start:
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%0 = fcmp fast oeq <2 x double> %a, %b
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; CHECK: fceq.d
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ret <2 x i1> %0
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}
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define <4 x i1> @testeq_v4f32(<4 x float> %a, <4 x float> %b) {
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start:
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%0 = fcmp fast oeq <4 x float> %a, %b
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; CHECK: fceq.w
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ret <4 x i1> %0
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}
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define <2 x i1> @testle_v2f64(<2 x double> %a, <2 x double> %b) {
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start:
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%0 = fcmp fast ole <2 x double> %a, %b
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; CHECK: fcle.d
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ret <2 x i1> %0
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}
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define <4 x i1> @testle_v4f32(<4 x float> %a, <4 x float> %b) {
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start:
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%0 = fcmp fast ole <4 x float> %a, %b
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; CHECK: fcle.w
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ret <4 x i1> %0
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}
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define <2 x i1> @testne_v2f64(<2 x double> %a, <2 x double> %b) {
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start:
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%0 = fcmp fast one <2 x double> %a, %b
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; CHECK: fcne.d
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ret <2 x i1> %0
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}
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define <4 x i1> @testne_v4f32(<4 x float> %a, <4 x float> %b) {
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start:
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%0 = fcmp fast one <4 x float> %a, %b
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; CHECK: fcne.w
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ret <4 x i1> %0
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}
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