c2b6c547dc
When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. Patch by jsji (Jinsong Ji) Differential Revision: https://reviews.llvm.org/D51506 llvm-svn: 341293
95 lines
3.1 KiB
LLVM
95 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; Make sure that a negative value for the compare-and-swap is zero extended
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; from i8/i16 to i32 since it will be compared for equality.
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; RUN: llc -mtriple=powerpc64le-linux-gnu -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=powerpc64le-linux-gnu -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-P7
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@str = private unnamed_addr constant [46 x i8] c"FAILED: __atomic_compare_exchange_n() failed.\00"
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@str.1 = private unnamed_addr constant [59 x i8] c"FAILED: __atomic_compare_exchange_n() set the wrong value.\00"
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@str.2 = private unnamed_addr constant [7 x i8] c"PASSED\00"
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define signext i32 @main() {
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; CHECK-LABEL: main:
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; CHECK: li 3, -32477
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; CHECK: li 6, 234
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; CHECK: sth 3, 46(1)
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; CHECK: lis 3, 0
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; CHECK: ori 4, 3, 33059
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; CHECK: sync
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; CHECK: .LBB0_1: # %L.entry
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; CHECK: lharx 3, 0, 5
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; CHECK: cmpw 4, 3
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; CHECK: bne 0, .LBB0_3
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; CHECK: sthcx. 6, 0, 5
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; CHECK: bne 0, .LBB0_1
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; CHECK: b .LBB0_4
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; CHECK: .LBB0_3: # %L.entry
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; CHECK: sthcx. 3, 0, 5
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; CHECK: .LBB0_4: # %L.entry
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; CHECK: cmplwi 3, 33059
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; CHECK: lwsync
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; CHECK: lhz 3, 46(1)
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; CHECK: cmplwi 3, 234
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;
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; CHECK-P7-LABEL: main:
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; CHECK-P7: li 3, -32477
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; CHECK-P7: lis 5, 0
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; CHECK-P7: li 7, 0
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; CHECK-P7: sth 3, 46(1)
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; CHECK-P7: li 6, 234
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; CHECK-P7: ori 5, 5, 33059
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; CHECK-P7: rlwinm 3, 4, 3, 27, 27
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; CHECK-P7: ori 7, 7, 65535
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; CHECK-P7: sync
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; CHECK-P7: slw 6, 6, 3
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; CHECK-P7: slw 8, 5, 3
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; CHECK-P7: slw 5, 7, 3
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; CHECK-P7: rldicr 4, 4, 0, 61
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; CHECK-P7: and 7, 6, 5
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; CHECK-P7: and 8, 8, 5
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; CHECK-P7: .LBB0_1: # %L.entry
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; CHECK-P7: lwarx 9, 0, 4
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; CHECK-P7: and 6, 9, 5
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; CHECK-P7: cmpw 0, 6, 8
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; CHECK-P7: bne 0, .LBB0_3
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; CHECK-P7: andc 9, 9, 5
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; CHECK-P7: or 9, 9, 7
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; CHECK-P7: stwcx. 9, 0, 4
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; CHECK-P7: bne 0, .LBB0_1
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; CHECK-P7: b .LBB0_4
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; CHECK-P7: .LBB0_3: # %L.entry
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; CHECK-P7: stwcx. 9, 0, 4
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; CHECK-P7: .LBB0_4: # %L.entry
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; CHECK-P7: srw 3, 6, 3
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; CHECK-P7: lwsync
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; CHECK-P7: cmplwi 3, 33059
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; CHECK-P7: lhz 3, 46(1)
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; CHECK-P7: cmplwi 3, 234
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L.entry:
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%value.addr = alloca i16, align 2
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store i16 -32477, i16* %value.addr, align 2
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%0 = cmpxchg i16* %value.addr, i16 -32477, i16 234 seq_cst seq_cst
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%1 = extractvalue { i16, i1 } %0, 1
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br i1 %1, label %L.B0000, label %L.B0003
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L.B0003: ; preds = %L.entry
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%puts = call i32 @puts(i8* getelementptr inbounds ([46 x i8], [46 x i8]* @str, i64 0, i64 0))
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ret i32 1
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L.B0000: ; preds = %L.entry
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%2 = load i16, i16* %value.addr, align 2
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%3 = icmp eq i16 %2, 234
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br i1 %3, label %L.B0001, label %L.B0005
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L.B0005: ; preds = %L.B0000
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%puts1 = call i32 @puts(i8* getelementptr inbounds ([59 x i8], [59 x i8]* @str.1, i64 0, i64 0))
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ret i32 1
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L.B0001: ; preds = %L.B0000
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%puts2 = call i32 @puts(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @str.2, i64 0, i64 0))
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ret i32 0
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}
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; Function Attrs: nounwind
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declare i32 @puts(i8* nocapture readonly) #0
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