c2b6c547dc
When doing some instruction scheduling work, we noticed some missing itineraries. Before we switch to machine scheduler, those missing itineraries might not have impact to actually scheduling, because we can still get same latency due to default values. With machine scheduler, however, itineraries will have impact to scheduling. eg: NumMicroOps will default to be 0 if there is NO itineraries for specific instruction class. And most of the instruction class with itineraries will have NumMicroOps default to 1. This will has impact on the count of RetiredMOps, affects the Pending/Available Queue, then causing different scheduling or suboptimal scheduling further. Patch by jsji (Jinsong Ji) Differential Revision: https://reviews.llvm.org/D51506 llvm-svn: 341293
166 lines
5.1 KiB
LLVM
166 lines
5.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
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define zeroext i32 @ReverseBits(i32 zeroext %n) {
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; CHECK-LABEL: ReverseBits:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lis 4, -21846
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; CHECK-NEXT: lis 5, 21845
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; CHECK-NEXT: slwi 6, 3, 1
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; CHECK-NEXT: srwi 3, 3, 1
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; CHECK-NEXT: ori 4, 4, 43690
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; CHECK-NEXT: ori 5, 5, 21845
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; CHECK-NEXT: and 4, 6, 4
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; CHECK-NEXT: and 3, 3, 5
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; CHECK-NEXT: lis 5, 13107
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: lis 4, -13108
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; CHECK-NEXT: ori 5, 5, 13107
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; CHECK-NEXT: slwi 6, 3, 2
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; CHECK-NEXT: ori 4, 4, 52428
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; CHECK-NEXT: srwi 3, 3, 2
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; CHECK-NEXT: and 4, 6, 4
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; CHECK-NEXT: and 3, 3, 5
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; CHECK-NEXT: lis 5, 3855
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: lis 4, -3856
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; CHECK-NEXT: ori 5, 5, 3855
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; CHECK-NEXT: slwi 6, 3, 4
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; CHECK-NEXT: ori 4, 4, 61680
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; CHECK-NEXT: srwi 3, 3, 4
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; CHECK-NEXT: and 4, 6, 4
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; CHECK-NEXT: and 3, 3, 5
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: rotlwi 4, 3, 24
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; CHECK-NEXT: rlwimi 4, 3, 8, 8, 15
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; CHECK-NEXT: rlwimi 4, 3, 8, 24, 31
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; CHECK-NEXT: rldicl 3, 4, 0, 32
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; CHECK-NEXT: clrldi 3, 3, 32
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; CHECK-NEXT: blr
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entry:
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%shr = lshr i32 %n, 1
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%and = and i32 %shr, 1431655765
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%and1 = shl i32 %n, 1
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%shl = and i32 %and1, -1431655766
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%or = or i32 %and, %shl
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%shr2 = lshr i32 %or, 2
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%and3 = and i32 %shr2, 858993459
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%and4 = shl i32 %or, 2
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%shl5 = and i32 %and4, -858993460
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%or6 = or i32 %and3, %shl5
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%shr7 = lshr i32 %or6, 4
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%and8 = and i32 %shr7, 252645135
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%and9 = shl i32 %or6, 4
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%shl10 = and i32 %and9, -252645136
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%or11 = or i32 %and8, %shl10
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%shr13 = lshr i32 %or11, 24
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%and14 = lshr i32 %or11, 8
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%shr15 = and i32 %and14, 65280
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%and17 = shl i32 %or11, 8
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%shl18 = and i32 %and17, 16711680
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%shl21 = shl i32 %or11, 24
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%or16 = or i32 %shl21, %shr13
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%or19 = or i32 %or16, %shr15
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%or22 = or i32 %or19, %shl18
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ret i32 %or22
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}
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define i64 @ReverseBits64(i64 %n) {
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; CHECK-LABEL: ReverseBits64:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lis 4, -21846
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; CHECK-NEXT: lis 5, 21845
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; CHECK-NEXT: lis 7, -13108
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; CHECK-NEXT: lis 8, 13107
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; CHECK-NEXT: ori 4, 4, 43690
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; CHECK-NEXT: ori 5, 5, 21845
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; CHECK-NEXT: ori 7, 7, 52428
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; CHECK-NEXT: ori 8, 8, 13107
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; CHECK-NEXT: sldi 4, 4, 32
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; CHECK-NEXT: sldi 5, 5, 32
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; CHECK-NEXT: oris 4, 4, 43690
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; CHECK-NEXT: oris 5, 5, 21845
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; CHECK-NEXT: sldi 6, 3, 1
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; CHECK-NEXT: rldicl 3, 3, 63, 1
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; CHECK-NEXT: ori 4, 4, 43690
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; CHECK-NEXT: ori 5, 5, 21845
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; CHECK-NEXT: sldi 7, 7, 32
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; CHECK-NEXT: sldi 8, 8, 32
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; CHECK-NEXT: and 4, 6, 4
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; CHECK-NEXT: and 3, 3, 5
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; CHECK-NEXT: lis 5, -3856
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; CHECK-NEXT: oris 6, 7, 52428
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; CHECK-NEXT: oris 7, 8, 13107
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; CHECK-NEXT: or 3, 3, 4
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; CHECK-NEXT: lis 4, 3855
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; CHECK-NEXT: ori 5, 5, 61680
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; CHECK-NEXT: ori 6, 6, 52428
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; CHECK-NEXT: ori 7, 7, 13107
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; CHECK-NEXT: ori 4, 4, 3855
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; CHECK-NEXT: sldi 8, 3, 2
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; CHECK-NEXT: rldicl 3, 3, 62, 2
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; CHECK-NEXT: and 6, 8, 6
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; CHECK-NEXT: and 3, 3, 7
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; CHECK-NEXT: sldi 5, 5, 32
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; CHECK-NEXT: sldi 4, 4, 32
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; CHECK-NEXT: or 3, 3, 6
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; CHECK-NEXT: oris 5, 5, 61680
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; CHECK-NEXT: oris 4, 4, 3855
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; CHECK-NEXT: sldi 6, 3, 4
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; CHECK-NEXT: ori 5, 5, 61680
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; CHECK-NEXT: ori 4, 4, 3855
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; CHECK-NEXT: rldicl 3, 3, 60, 4
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; CHECK-NEXT: and 5, 6, 5
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; CHECK-NEXT: and 3, 3, 4
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; CHECK-NEXT: or 3, 3, 5
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; CHECK-NEXT: rldicl 4, 3, 32, 32
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; CHECK-NEXT: rlwinm 5, 3, 24, 0, 31
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; CHECK-NEXT: rlwinm 6, 4, 24, 0, 31
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; CHECK-NEXT: rlwimi 5, 3, 8, 8, 15
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; CHECK-NEXT: rlwimi 5, 3, 8, 24, 31
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; CHECK-NEXT: rlwimi 6, 4, 8, 8, 15
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; CHECK-NEXT: rlwimi 6, 4, 8, 24, 31
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; CHECK-NEXT: sldi 3, 5, 32
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; CHECK-NEXT: or 3, 3, 6
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; CHECK-NEXT: blr
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entry:
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%shr = lshr i64 %n, 1
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%and = and i64 %shr, 6148914691236517205
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%and1 = shl i64 %n, 1
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%shl = and i64 %and1, -6148914691236517206
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%or = or i64 %and, %shl
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%shr2 = lshr i64 %or, 2
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%and3 = and i64 %shr2, 3689348814741910323
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%and4 = shl i64 %or, 2
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%shl5 = and i64 %and4, -3689348814741910324
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%or6 = or i64 %and3, %shl5
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%shr7 = lshr i64 %or6, 4
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%and8 = and i64 %shr7, 1085102592571150095
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%and9 = shl i64 %or6, 4
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%shl10 = and i64 %and9, -1085102592571150096
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%or11 = or i64 %and8, %shl10
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%shr13 = lshr i64 %or11, 56
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%and14 = lshr i64 %or11, 40
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%shr15 = and i64 %and14, 65280
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%and17 = lshr i64 %or11, 24
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%shr18 = and i64 %and17, 16711680
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%and20 = lshr i64 %or11, 8
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%shr21 = and i64 %and20, 4278190080
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%and23 = shl i64 %or11, 8
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%shl24 = and i64 %and23, 1095216660480
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%and26 = shl i64 %or11, 24
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%shl27 = and i64 %and26, 280375465082880
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%and29 = shl i64 %or11, 40
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%shl30 = and i64 %and29, 71776119061217280
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%shl33 = shl i64 %or11, 56
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%or16 = or i64 %shl33, %shr13
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%or19 = or i64 %or16, %shr15
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%or22 = or i64 %or19, %shr18
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%or25 = or i64 %or22, %shr21
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%or28 = or i64 %or25, %shl24
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%or31 = or i64 %or28, %shl27
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%or34 = or i64 %or31, %shl30
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ret i64 %or34
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}
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