1dc0a8fb18
Summary:
When lowering global address, lower the base as a TargetGlobal first then
create an SDNode for the offset separately and chain it to the address calculation
This optimization will create a DAG where the base address of a global access will
be reused between different access. The offset can later be folded into the immediate
part of the memory access instruction.
With this optimization we generate:
lui a0, %hi(s)
addi a0, a0, %lo(s) ; shared base address.
addi a1, zero, 20 ; 2 instructions per access.
sw a1, 44(a0)
addi a1, zero, 10
sw a1, 8(a0)
addi a1, zero, 30
sw a1, 80(a0)
Instead of:
lui a0, %hi(s+44) ; 3 instructions per access.
addi a1, zero, 20
sw a1, %lo(s+44)(a0)
lui a0, %hi(s+8)
addi a1, zero, 10
sw a1, %lo(s+8)(a0)
lui a0, %hi(s+80)
addi a1, zero, 30
sw a1, %lo(s+80)(a0)
Which will save one instruction per access.
Reviewers: asb, apazos
Reviewed By: asb
Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, apazos, asb, llvm-commits
Differential Revision: https://reviews.llvm.org/D46989
llvm-svn: 332641
134 lines
4.0 KiB
LLVM
134 lines
4.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IF %s
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define float @flw(float *%a) nounwind {
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; RV32IF-LABEL: flw:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: flw ft0, 12(a0)
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; RV32IF-NEXT: flw ft1, 0(a0)
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; RV32IF-NEXT: fadd.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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%1 = load float, float* %a
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%2 = getelementptr float, float* %a, i32 3
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%3 = load float, float* %2
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; Use both loaded values in an FP op to ensure an flw is used, even for the
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; soft float ABI
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%4 = fadd float %1, %3
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ret float %4
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}
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define void @fsw(float *%a, float %b, float %c) nounwind {
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; Use %b and %c in an FP op to ensure floating point registers are used, even
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; for the soft float ABI
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; RV32IF-LABEL: fsw:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a2
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; RV32IF-NEXT: fmv.w.x ft1, a1
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; RV32IF-NEXT: fadd.s ft0, ft1, ft0
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; RV32IF-NEXT: fsw ft0, 32(a0)
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; RV32IF-NEXT: fsw ft0, 0(a0)
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; RV32IF-NEXT: ret
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%1 = fadd float %b, %c
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store float %1, float* %a
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%2 = getelementptr float, float* %a, i32 8
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store float %1, float* %2
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ret void
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}
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; Check load and store to a global
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@G = global float 0.0
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define float @flw_fsw_global(float %a, float %b) nounwind {
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; Use %a and %b in an FP op to ensure floating point registers are used, even
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; for the soft float ABI
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; RV32IF-LABEL: flw_fsw_global:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fadd.s ft0, ft1, ft0
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; RV32IF-NEXT: lui a0, %hi(G)
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; RV32IF-NEXT: flw ft1, %lo(G)(a0)
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; RV32IF-NEXT: fsw ft0, %lo(G)(a0)
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; RV32IF-NEXT: addi a0, a0, %lo(G)
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; RV32IF-NEXT: flw ft1, 36(a0)
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; RV32IF-NEXT: fsw ft0, 36(a0)
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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%1 = fadd float %a, %b
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%2 = load volatile float, float* @G
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store float %1, float* @G
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%3 = getelementptr float, float* @G, i32 9
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%4 = load volatile float, float* %3
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store float %1, float* %3
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ret float %1
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}
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; Ensure that 1 is added to the high 20 bits if bit 11 of the low part is 1
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define float @flw_fsw_constant(float %a) nounwind {
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; RV32IF-LABEL: flw_fsw_constant:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: fmv.w.x ft0, a0
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; RV32IF-NEXT: lui a0, 912092
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; RV32IF-NEXT: flw ft1, -273(a0)
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; RV32IF-NEXT: fadd.s ft0, ft0, ft1
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; RV32IF-NEXT: fsw ft0, -273(a0)
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: ret
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%1 = inttoptr i32 3735928559 to float*
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%2 = load volatile float, float* %1
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%3 = fadd float %a, %2
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store float %3, float* %1
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ret float %3
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}
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declare void @notdead(i8*)
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define float @flw_stack(float %a) nounwind {
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; RV32IF-LABEL: flw_stack:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: addi sp, sp, -16
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; RV32IF-NEXT: sw ra, 12(sp)
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; RV32IF-NEXT: sw s1, 8(sp)
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; RV32IF-NEXT: mv s1, a0
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; RV32IF-NEXT: addi a0, sp, 4
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; RV32IF-NEXT: call notdead
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; RV32IF-NEXT: fmv.w.x ft0, s1
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; RV32IF-NEXT: flw ft1, 4(sp)
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; RV32IF-NEXT: fadd.s ft0, ft1, ft0
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; RV32IF-NEXT: fmv.x.w a0, ft0
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; RV32IF-NEXT: lw s1, 8(sp)
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; RV32IF-NEXT: lw ra, 12(sp)
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; RV32IF-NEXT: addi sp, sp, 16
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; RV32IF-NEXT: ret
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%1 = alloca float, align 4
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%2 = bitcast float* %1 to i8*
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call void @notdead(i8* %2)
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%3 = load float, float* %1
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%4 = fadd float %3, %a ; force load in to FPR32
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ret float %4
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}
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define void @fsw_stack(float %a, float %b) nounwind {
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; RV32IF-LABEL: fsw_stack:
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; RV32IF: # %bb.0:
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; RV32IF-NEXT: addi sp, sp, -16
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; RV32IF-NEXT: sw ra, 12(sp)
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; RV32IF-NEXT: fmv.w.x ft0, a1
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; RV32IF-NEXT: fmv.w.x ft1, a0
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; RV32IF-NEXT: fadd.s ft0, ft1, ft0
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; RV32IF-NEXT: fsw ft0, 8(sp)
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; RV32IF-NEXT: addi a0, sp, 8
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; RV32IF-NEXT: call notdead
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; RV32IF-NEXT: lw ra, 12(sp)
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; RV32IF-NEXT: addi sp, sp, 16
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; RV32IF-NEXT: ret
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%1 = fadd float %a, %b ; force store from FPR32
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%2 = alloca float, align 4
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store float %1, float* %2
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%3 = bitcast float* %2 to i8*
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call void @notdead(i8* %3)
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ret void
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}
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