d58bd8dc4a
To do this: 1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer split the symbol. 2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer split the symbol. 3. Let PseudoCALL match direct call with target operand TargetGlobalAddress and TargetExternalSymbol. Differential Revision: https://reviews.llvm.org/D44885 llvm-svn: 330827
176 lines
4.3 KiB
LLVM
176 lines
4.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32I %s
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; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IM %s
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define i32 @square(i32 %a) nounwind {
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; RV32I-LABEL: square:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: mv a1, a0
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; RV32I-NEXT: call __mulsi3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: square:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: mul a0, a0, a0
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; RV32IM-NEXT: ret
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%1 = mul i32 %a, %a
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ret i32 %1
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}
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define i32 @mul(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: mul:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: call __mulsi3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: mul:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: mul a0, a0, a1
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; RV32IM-NEXT: ret
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%1 = mul i32 %a, %b
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ret i32 %1
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}
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define i32 @mul_constant(i32 %a) nounwind {
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; RV32I-LABEL: mul_constant:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: addi a1, zero, 5
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; RV32I-NEXT: call __mulsi3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: mul_constant:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: addi a1, zero, 5
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; RV32IM-NEXT: mul a0, a0, a1
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; RV32IM-NEXT: ret
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%1 = mul i32 %a, 5
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ret i32 %1
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}
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define i32 @mul_pow2(i32 %a) nounwind {
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; RV32I-LABEL: mul_pow2:
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; RV32I: # %bb.0:
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; RV32I-NEXT: slli a0, a0, 3
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: mul_pow2:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: slli a0, a0, 3
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; RV32IM-NEXT: ret
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%1 = mul i32 %a, 8
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ret i32 %1
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}
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define i64 @mul64(i64 %a, i64 %b) nounwind {
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; RV32I-LABEL: mul64:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: call __muldi3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: mul64:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: mul a3, a0, a3
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; RV32IM-NEXT: mulhu a4, a0, a2
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; RV32IM-NEXT: add a3, a4, a3
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; RV32IM-NEXT: mul a1, a1, a2
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; RV32IM-NEXT: add a1, a3, a1
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; RV32IM-NEXT: mul a0, a0, a2
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; RV32IM-NEXT: ret
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%1 = mul i64 %a, %b
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ret i64 %1
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}
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define i64 @mul64_constant(i64 %a) nounwind {
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; RV32I-LABEL: mul64_constant:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: addi a2, zero, 5
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; RV32I-NEXT: mv a3, zero
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; RV32I-NEXT: call __muldi3
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: mul64_constant:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: addi a2, zero, 5
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; RV32IM-NEXT: mul a1, a1, a2
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; RV32IM-NEXT: mulhu a3, a0, a2
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; RV32IM-NEXT: add a1, a3, a1
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; RV32IM-NEXT: mul a0, a0, a2
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; RV32IM-NEXT: ret
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%1 = mul i64 %a, 5
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ret i64 %1
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}
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define i32 @mulhs(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: mulhs:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: mv a2, a1
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; RV32I-NEXT: srai a1, a0, 31
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; RV32I-NEXT: srai a3, a2, 31
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; RV32I-NEXT: call __muldi3
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; RV32I-NEXT: mv a0, a1
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: mulhs:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: mulh a0, a0, a1
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; RV32IM-NEXT: ret
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%1 = sext i32 %a to i64
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%2 = sext i32 %b to i64
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%3 = mul i64 %1, %2
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%4 = lshr i64 %3, 32
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%5 = trunc i64 %4 to i32
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ret i32 %5
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}
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define i32 @mulhu(i32 %a, i32 %b) nounwind {
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; RV32I-LABEL: mulhu:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi sp, sp, -16
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; RV32I-NEXT: sw ra, 12(sp)
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; RV32I-NEXT: mv a2, a1
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; RV32I-NEXT: mv a1, zero
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; RV32I-NEXT: mv a3, zero
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; RV32I-NEXT: call __muldi3
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; RV32I-NEXT: mv a0, a1
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; RV32I-NEXT: lw ra, 12(sp)
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; RV32I-NEXT: addi sp, sp, 16
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; RV32I-NEXT: ret
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;
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; RV32IM-LABEL: mulhu:
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; RV32IM: # %bb.0:
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; RV32IM-NEXT: mulhu a0, a0, a1
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; RV32IM-NEXT: ret
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%1 = zext i32 %a to i64
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%2 = zext i32 %b to i64
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%3 = mul i64 %1, %2
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%4 = lshr i64 %3, 32
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%5 = trunc i64 %4 to i32
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ret i32 %5
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}
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