39 lines
1.0 KiB
LLVM
39 lines
1.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck %s -check-prefix=RV32I
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; These IR sequences will generate ISD::ROTL and ISD::ROTR nodes, that the
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; RISC-V backend must be able to select
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define i32 @rotl(i32 %x, i32 %y) {
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; RV32I-LABEL: rotl:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a2, zero, 32
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; RV32I-NEXT: sub a2, a2, a1
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; RV32I-NEXT: sll a1, a0, a1
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; RV32I-NEXT: srl a0, a0, a2
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; RV32I-NEXT: or a0, a1, a0
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; RV32I-NEXT: ret
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%z = sub i32 32, %y
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%b = shl i32 %x, %y
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%c = lshr i32 %x, %z
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%d = or i32 %b, %c
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ret i32 %d
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}
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define i32 @rotr(i32 %x, i32 %y) {
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; RV32I-LABEL: rotr:
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; RV32I: # %bb.0:
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; RV32I-NEXT: addi a2, zero, 32
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; RV32I-NEXT: sub a2, a2, a1
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; RV32I-NEXT: srl a1, a0, a1
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; RV32I-NEXT: sll a0, a0, a2
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; RV32I-NEXT: or a0, a1, a0
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; RV32I-NEXT: ret
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%z = sub i32 32, %y
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%b = lshr i32 %x, %y
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%c = shl i32 %x, %z
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%d = or i32 %b, %c
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ret i32 %d
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}
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