e1687a89e8
LLVM normally prefers to minimize the number of bits set in an AND immediate, but that doesn't always match the available ARM instructions. In Thumb1 mode, prefer uxtb or uxth where possible; otherwise, prefer a two-instruction sequence movs+ands or movs+bics. Some potential improvements outlined in ARMTargetLowering::targetShrinkDemandedConstant, but seems to work pretty well already. The ARMISelDAGToDAG fix ensures we don't generate an invalid UBFX instruction due to a larger-than-expected mask. (It's orthogonal, in some sense, but as far as I can tell it's either impossible or nearly impossible to reproduce the bug without this change.) According to my testing, this seems to consistently improve codesize by a small amount by forming bic more often for ISD::AND with an immediate. Differential Revision: https://reviews.llvm.org/D50030 llvm-svn: 339472
134 lines
2.8 KiB
LLVM
134 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv6-eabi %s -o - | FileCheck %s
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define i32 @test1(i32 %x) {
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; CHECK-LABEL: test1:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: lsls r0, r0, #20
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; CHECK-NEXT: lsrs r0, r0, #22
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i32 %x, 2
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%shr = and i32 %0, 1023
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ret i32 %shr
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}
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define i32 @test2(i32 %x) {
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; CHECK-LABEL: test2:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: lsrs r1, r0, #2
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; CHECK-NEXT: ldr r0, .LCPI1_0
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; CHECK-NEXT: ands r0, r1
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; CHECK-NEXT: bx lr
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: @ %bb.1:
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; CHECK-NEXT: .LCPI1_0:
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; CHECK-NEXT: .long 1022 @ 0x3fe
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entry:
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%0 = lshr i32 %x, 2
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%shr = and i32 %0, 1022
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ret i32 %shr
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}
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define i32 @test3(i32 %x) {
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; CHECK-LABEL: test3:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: lsrs r0, r0, #2
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; CHECK-NEXT: uxtb r0, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i32 %x, 2
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%shr = and i32 %0, 255
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ret i32 %shr
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}
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define i32 @test4(i32 %x) {
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; CHECK-LABEL: test4:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: lsls r0, r0, #4
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; CHECK-NEXT: movs r1, #112
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; CHECK-NEXT: bics r0, r1
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; CHECK-NEXT: bx lr
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entry:
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%0 = shl i32 %x, 4
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%shr = and i32 %0, -128
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ret i32 %shr
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}
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define i32 @test5(i32 %x) {
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; CHECK-LABEL: test5:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: lsls r0, r0, #31
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; CHECK-NEXT: lsrs r0, r0, #2
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; CHECK-NEXT: bx lr
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entry:
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%0 = shl i32 %x, 29
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%shr = and i32 %0, 536870912
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ret i32 %shr
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}
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define i32 @test6(i32 %x) {
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; CHECK-LABEL: test6:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: movs r1, #5
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; CHECK-NEXT: lsls r1, r1, #29
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; CHECK-NEXT: lsls r0, r0, #29
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; CHECK-NEXT: ands r0, r1
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; CHECK-NEXT: bx lr
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entry:
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%0 = shl i32 %x, 29
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%shr = and i32 %0, 2684354560
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ret i32 %shr
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}
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define i32 @test7(i32 %x) {
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; CHECK-LABEL: test7:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: lsrs r1, r0, #29
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; CHECK-NEXT: movs r0, #4
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; CHECK-NEXT: ands r0, r1
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i32 %x, 29
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%shr = and i32 %0, 4
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ret i32 %shr
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}
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define i32 @test8(i32 %x) {
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; CHECK-LABEL: test8:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: lsrs r1, r0, #29
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; CHECK-NEXT: movs r0, #5
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; CHECK-NEXT: ands r0, r1
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; CHECK-NEXT: bx lr
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entry:
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%0 = lshr i32 %x, 29
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%shr = and i32 %0, 5
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ret i32 %shr
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}
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define i32 @test9(i32 %x) {
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; CHECK-LABEL: test9:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: lsrs r0, r0, #2
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; CHECK-NEXT: movs r1, #1
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; CHECK-NEXT: bics r0, r1
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; CHECK-NEXT: bx lr
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entry:
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%and = lshr i32 %x, 2
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%shr = and i32 %and, 1073741822
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ret i32 %shr
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}
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define i32 @test10(i32 %x) {
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; CHECK-LABEL: test10:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: lsls r0, r0, #2
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; CHECK-NEXT: uxtb r0, r0
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; CHECK-NEXT: bx lr
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entry:
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%0 = shl i32 %x, 2
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%shr = and i32 %0, 255
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ret i32 %shr
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}
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