Justin Hibbits 4fa4fa6a73 Complete the SPE instruction set patterns ...

This is the lead-up to having SPE codegen.  Add the rest of the
instructions, along with MC tests.

Differential Revision:  https://reviews.llvm.org/D44829

llvm-svn: 337346

2018-07-18 04:24:57 +00:00

..

dcbt.txt

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lit.local.cfg

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ppc32-extpid-e500.txt

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ppc64-encoding-4xx.txt

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ppc64-encoding-6xx.txt

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ppc64-encoding-bookII.txt

[PowerPC] Fix incorrectly encoded wait instruction

2018-06-25 19:28:27 +00:00

ppc64-encoding-bookIII.txt

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ppc64-encoding-e500.txt

Complete the SPE instruction set patterns

2018-07-18 04:24:57 +00:00

ppc64-encoding-ext.txt

[PowerPC] Enable printing instructions using aliases

2015-04-23 18:30:38 +00:00

ppc64-encoding-fp.txt

[Power9] Add new instructions for floating point status and control registers.

2017-08-28 18:46:01 +00:00

ppc64-encoding-p8vector.txt

[PPC64] Add vector pack/unpack support from ISA 2.07

2015-05-16 01:02:12 +00:00

ppc64-encoding-p9vector.txt

[PPC] Change the register constraint of the first source operand of instruction mtvsrdd to g8rc_nox0

2017-05-11 22:17:35 +00:00

ppc64-encoding-vmx.txt

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ppc64-encoding.txt

[Power9] Add missing Power9 instructions.

2017-09-19 15:22:36 +00:00

ppc64-operands.txt

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ppc64le-encoding.txt

[Power9] Added support for the modsw, moduw, modsd, modud hardware instructions.

2017-06-12 17:58:42 +00:00

qpx.txt

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vsx.txt

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