Simon Dardis 437153bb80 [mips] Correct the predicates of the cache and pref instructions ...

Reviewers: atanasyan, abeserminji, smaksimovic

Differential Revision: https://reviews.llvm.org/D46949

llvm-svn: 332970

2018-05-22 10:55:05 +00:00

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invalid-mips1-wrong-error.s

[mips] Correct the predicates of the load/store (double)word for coprocessor 3.

2018-04-12 14:41:38 +00:00

invalid-mips1.s

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invalid-mips2-wrong-error.s

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invalid-mips2.s

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invalid-mips4-wrong-error.s

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invalid-mips4.s

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invalid-mips5-wrong-error.s

[mips] Show an error if register number is out of range

2018-04-24 16:14:00 +00:00

invalid-mips5.s

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invalid-mips32-wrong-error.s

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invalid-mips32.s

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invalid-mips32r2.s

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invalid.s

[mips] Accept 32-bit offsets for lh and lhu commands

2018-05-10 16:01:18 +00:00

relocations.s

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valid.s

[mips] Correct the predicates of the cache and pref instructions

2018-05-22 10:55:05 +00:00