Alex Bradbury fea4ac01c5 [RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands ...

Standardise on check lines:
* CHECK-ASM
* CHECK-OBJ
* CHECK-ASM-AND-OBJ

This allows for the addition of tests involving symbol operands, which will
not result in identical instructions in both assembly and disassembled object 
output.

This commit doesn't exploit this reworking to increase test coverage of symbol
operands - that will come in a future patch.

llvm-svn: 341546

2018-09-06 13:41:04 +00:00

..

cnop.s

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compress-cjal.s

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compress-rv32d.s

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compress-rv32f.s

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compress-rv32i.s

[RISCV] Add c.mv rs1, rs2 pattern for addi rs1, rs2, 0

2018-04-12 19:22:40 +00:00

compress-rv64i.s

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compressed-relocations.s

[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced

2018-05-18 06:42:21 +00:00

csr-aliases.s

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data-directives-invalid.s

[RISCV] Add support for .half, .hword, .word, .dword directives

2018-05-17 05:58:08 +00:00

data-directives-valid.s

[RISCV] Add support for .half, .hword, .word, .dword directives

2018-05-17 05:58:08 +00:00

elf-flags.s

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elf-header.s

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fixups-compressed.s

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fixups-diagnostics.s

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fixups-expr.s

[RISCV] Add symbol diff relocation support for RISC-V

2018-05-23 12:36:18 +00:00

fixups.s

[RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table

2018-05-30 01:16:36 +00:00

function-call-invalid.s

[RISCV] Support "call" pseudoinstruction in the MC layer

2018-04-25 14:18:55 +00:00

function-call.s

[RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table

2018-05-30 01:16:36 +00:00

hilo-constaddr-expr.s

[RISCV] Add symbol diff relocation support for RISC-V

2018-05-23 12:36:18 +00:00

hilo-constaddr.s

[RISCV] Add symbol diff relocation support for RISC-V

2018-05-23 12:36:18 +00:00

linker-relaxation.s

[RISCV] Support resolving fixup_riscv_call and add to MCFixupKindInfo table

2018-05-30 01:16:36 +00:00

lit.local.cfg

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lla-invalid.s

[RISCV] Add "lla" pseudo-instruction to assembler

2018-08-09 07:08:20 +00:00

option-invalid.s

[RISCV] Support .option rvc and norvc assembler directives

2018-05-11 17:30:28 +00:00

option-rvc.s

[RISCV] Support .option rvc and norvc assembler directives

2018-05-11 17:30:28 +00:00

priv-invalid.s

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priv-valid.s

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relocations.s

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rv32-relaxation.s

[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced

2018-05-18 06:42:21 +00:00

rv32a-invalid.s

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rv32a-valid.s

[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands

2018-09-06 13:41:04 +00:00

rv32c-aliases-valid.s

[RISC-V] Fixed alias for addi x2, x2, 0

2018-08-09 20:51:53 +00:00

rv32c-fuzzed-invalid.s

[RISCV] Fixed Assertion`Kind == Immediate && "Invalid type access!"' failed.

2018-08-24 23:47:49 +00:00

rv32c-invalid.s

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rv32c-only-valid.s

[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands

2018-09-06 13:41:04 +00:00

rv32c-valid.s

[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands

2018-09-06 13:41:04 +00:00

rv32d-invalid.s

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rv32d-valid.s

[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands

2018-09-06 13:41:04 +00:00

rv32dc-invalid.s

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rv32dc-valid.s

[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands

2018-09-06 13:41:04 +00:00

rv32f-invalid.s

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rv32f-valid.s

[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands

2018-09-06 13:41:04 +00:00

rv32fc-invalid.s

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rv32fc-valid.s

[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands

2018-09-06 13:41:04 +00:00

rv32i-aliases-invalid.s

[RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], sra[w], slt and sltu with immediate

2018-08-08 14:45:44 +00:00

rv32i-aliases-valid.s

[RISCV] AsmParser support for the li pseudo instruction

2018-06-07 15:35:47 +00:00

rv32i-invalid.s

[RISCV] Fixed SmallVector.h Assertion `idx < size()'

2018-08-30 19:43:19 +00:00

rv32i-valid.s

[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands

2018-09-06 13:41:04 +00:00

rv32m-invalid.s

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rv32m-valid.s

[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands

2018-09-06 13:41:04 +00:00

rv64-relaxation.s

[RISCV] Add WasForced parameter to MCAsmBackend::fixupNeedsRelaxationAdvanced

2018-05-18 06:42:21 +00:00

rv64a-invalid.s

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rv64a-valid.s

[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands

2018-09-06 13:41:04 +00:00

rv64c-aliases-valid.s

[RISCV] AsmParser support for the li pseudo instruction

2018-06-07 15:35:47 +00:00

rv64c-invalid.s

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rv64c-valid.s

[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands

2018-09-06 13:41:04 +00:00

rv64d-aliases-valid.s

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rv64d-invalid.s

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rv64d-valid.s

[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands

2018-09-06 13:41:04 +00:00

rv64dc-valid.s

[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands

2018-09-06 13:41:04 +00:00

rv64f-aliases-valid.s

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rv64f-invalid.s

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rv64f-valid.s

[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands

2018-09-06 13:41:04 +00:00

rv64i-aliases-invalid.s

[RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], sra[w], slt and sltu with immediate

2018-08-08 14:45:44 +00:00

rv64i-aliases-valid.s

[RISCV] Add InstAlias definitions for add[w], and, xor, or, sll[w], srl[w], sra[w], slt and sltu with immediate

2018-08-08 14:45:44 +00:00

rv64i-invalid.s

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rv64i-valid.s

[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands

2018-09-06 13:41:04 +00:00

rv64m-valid.s

[RISCV][NFC] Rework test/MC/RISCV/rv{32,64}* to allow testing of symbol operands

2018-09-06 13:41:04 +00:00

rvd-aliases-valid.s

[RISCV] Add InstAlias definitions for fgt.{s|d}, fge.{s|d}

2018-06-20 14:03:02 +00:00

rvf-aliases-valid.s

[RISCV] Accept fmv.s.x and fmv.x.s as mnemonic aliases for fmv.w.x and fmv.x.w

2018-06-20 18:42:25 +00:00

rvi-aliases-valid.s

[RISCV] Fix r341050

2018-08-30 10:39:30 +00:00

rvi-pseudos.s

[RISCV] Add "lla" pseudo-instruction to assembler

2018-08-09 07:08:20 +00:00

tail-call-invalid.s

[RISCV] Implement MC layer support for the tail pseudoinstruction

2018-05-17 17:31:27 +00:00

tail-call.s

[RISCV] Tail calls don't need to save return address

2018-06-21 14:37:09 +00:00