e538fc74d4
Summary: We should always be able to accept AVX512 registers and instructions in llvm-mc. The only subtarget mode that should be checked is 16-bit vs 32-bit vs 64-bit mode. I've also removed all the mattr/mcpu lines from test RUN lines to be consistent with this. Most were due to AVX512, but a few were for other features. Fixes PR36202 Reviewers: RKSimon, echristo, bkramer Reviewed By: echristo Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D42824 llvm-svn: 324106
30 lines
676 B
ArmAsm
30 lines
676 B
ArmAsm
// RUN: llvm-mc -triple x86_64-unknown-unknown -x86-asm-syntax=intel %s | FileCheck %s
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// Check that we deduce unsized memory operands in the general, unambiguous, case.
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// We can't deduce xword memory operands, because there is no instruction
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// unambiguously accessing 80-bit memory.
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// CHECK: movb %al, (%rax)
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mov [rax], al
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// CHECK: movw %ax, (%rax)
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mov [rax], ax
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// CHECK: movl %eax, (%rax)
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mov [rax], eax
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// CHECK: movq %rax, (%rax)
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mov [rax], rax
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// CHECK: movdqa %xmm0, (%rax)
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movdqa [rax], xmm0
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// CHECK: vmovdqa %ymm0, (%rax)
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vmovdqa [rax], ymm0
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// CHECK: vaddps (%rax), %zmm1, %zmm1
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vaddps zmm1, zmm1, [rax]
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// CHECK: leal 1(%r15d), %r9d
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lea r9d, [r15d+1]
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