c4c6b548c5
CodeGenPrepare pass move extension instructions close to load instructions in different BB, so they can be combined later. But the extension instructions can't move through logical and shift instructions in current implementation. This patch enables this enhancement, so we can eliminate more extension instructions. Differential Revision: https://reviews.llvm.org/D45537 This is re-commit of r331783, which was reverted by r333305. The performance regression was caused by some unlucky alignment, not a code generation problem. llvm-svn: 334049
129 lines
3.6 KiB
LLVM
129 lines
3.6 KiB
LLVM
; RUN: opt < %s -codegenprepare -S -mtriple=x86_64-unknown-unknown | FileCheck %s
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@a = global [10 x i8] zeroinitializer, align 1
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declare void @foo()
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; ext(and(ld, cst)) -> and(ext(ld), ext(cst))
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define void @test1(i32* %p, i32 %ll) {
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; CHECK-LABEL: @test1
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; CHECK-NEXT: entry:
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; CHECK-NEXT: load
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; CHECK-NEXT: zext
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; CHECK-NEXT: and
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entry:
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%tmp = load i8, i8* getelementptr inbounds ([10 x i8], [10 x i8]* @a, i64 0, i64 0), align 1
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%and = and i8 %tmp, 60
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%cmp = icmp ugt i8 %and, 20
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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%conv2 = zext i8 %and to i32
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%add = add nsw i32 %conv2, %ll
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store i32 %add, i32* %p, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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tail call void @foo()
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ret void
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}
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; ext(or(ld, cst)) -> or(ext(ld), ext(cst))
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define void @test2(i32* %p, i32 %ll) {
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; CHECK-LABEL: @test2
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; CHECK-NEXT: entry:
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; CHECK-NEXT: load
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; CHECK-NEXT: zext
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; CHECK-NEXT: or
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entry:
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%tmp = load i8, i8* getelementptr inbounds ([10 x i8], [10 x i8]* @a, i64 0, i64 0), align 1
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%or = or i8 %tmp, 60
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%cmp = icmp ugt i8 %or, 20
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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%conv2 = zext i8 %or to i32
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%add = add nsw i32 %conv2, %ll
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store i32 %add, i32* %p, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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tail call void @foo()
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ret void
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}
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; ext(and(shl(ld, cst), cst)) -> and(shl(ext(ld), ext(cst)), ext(cst))
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define void @test3(i32* %p, i32 %ll) {
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; CHECK-LABEL: @test3
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; CHECK-NEXT: entry:
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; CHECK-NEXT: load
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; CHECK-NEXT: zext
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; CHECK-NEXT: shl
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; CHECK-NEXT: and
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entry:
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%tmp = load i8, i8* getelementptr inbounds ([10 x i8], [10 x i8]* @a, i64 0, i64 0), align 1
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%shl = shl i8 %tmp, 2
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%and = and i8 %shl, 60
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%cmp = icmp ugt i8 %and, 20
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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%conv2 = zext i8 %and to i32
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%add = add nsw i32 %conv2, %ll
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store i32 %add, i32* %p, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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tail call void @foo()
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ret void
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}
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; zext(shrl(ld, cst)) -> shrl(zext(ld), zext(cst))
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define void @test4(i32* %p, i32 %ll) {
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; CHECK-LABEL: @test4
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; CHECK-NEXT: entry:
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; CHECK-NEXT: load
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; CHECK-NEXT: zext
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; CHECK-NEXT: lshr
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entry:
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%tmp = load i8, i8* getelementptr inbounds ([10 x i8], [10 x i8]* @a, i64 0, i64 0), align 1
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%lshr = lshr i8 %tmp, 2
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%cmp = icmp ugt i8 %lshr, 20
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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%conv2 = zext i8 %lshr to i32
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%add = add nsw i32 %conv2, %ll
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store i32 %add, i32* %p, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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tail call void @foo()
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ret void
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}
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; ext(xor(ld, cst)) -> xor(ext(ld), ext(cst))
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define void @test5(i32* %p, i32 %ll) {
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; CHECK-LABEL: @test5
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; CHECK-NEXT: entry:
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; CHECK-NEXT: load
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; CHECK-NEXT: zext
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; CHECK-NEXT: xor
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entry:
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%tmp = load i8, i8* getelementptr inbounds ([10 x i8], [10 x i8]* @a, i64 0, i64 0), align 1
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%xor = xor i8 %tmp, 60
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%cmp = icmp ugt i8 %xor, 20
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br i1 %cmp, label %if.then, label %if.end
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if.then: ; preds = %entry
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%conv2 = zext i8 %xor to i32
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%add = add nsw i32 %conv2, %ll
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store i32 %add, i32* %p, align 4
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br label %if.end
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if.end: ; preds = %if.then, %entry
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tail call void @foo()
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ret void
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}
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