d874c3a480
LSR reassociates small constants that fit into add immediate operands as unfolded offset. Since unfolded offset is not combined with loop-invariant registers, LSR does not consider solutions that bump invariant registers by these constants outside the loop. llvm-svn: 341835
152 lines
6.0 KiB
LLVM
152 lines
6.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
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; LSR doesn't consider bumping a pointer by constants outside the loop when the
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; constants fit as immediate add operands. The constants are re-associated as an
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; unfolded offset rather than a register and are not combined later with
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; loop-invariant registers. For large-enough constants LSR produces better
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; solutions for these test cases, with test1 switching from:
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;
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; The chosen solution requires 2 instructions 2 regs, with addrec cost 1, plus 1 scale cost, plus 4 imm cost, plus 1 setup cost:
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; LSR Use: Kind=ICmpZero, Offsets={0}, widest fixup type: i64
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; -7 + reg({(7 + %start)<nsw>,+,1}<nsw><%for.body>)
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; LSR Use: Kind=Address of float in addrspace(0), Offsets={0}, widest fixup type: float*
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; reg(%arr) + 4*reg({(7 + %start)<nsw>,+,1}<nsw><%for.body>)
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;
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; to:
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;
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; The chosen solution requires 1 instruction 2 regs, with addrec cost 1, plus 1 scale cost, plus 1 setup cost:
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; LSR Use: Kind=ICmpZero, Offsets={0}, widest fixup type: i64
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; reg({%start,+,1}<nsw><%for.body>)
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; LSR Use: Kind=Address of float in addrspace(0), Offsets={0}, widest fixup type: float*
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; reg((88888 + %arr)) + 4*reg({%start,+,1}<nsw><%for.body>)
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;
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; and test2 switching from:
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;
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; The chosen solution requires 2 instructions 2 regs, with addrec cost 1, plus 1 base add, plus 1 scale cost:
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; LSR Use: Kind=ICmpZero, Offsets={0}, widest fixup type: i64
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; reg({%start,+,1}<nsw><%for.body>)
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; LSR Use: Kind=Basic, Offsets={0}, widest fixup type: i64
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; reg({%start,+,1}<nsw><%for.body>)
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; LSR Use: Kind=Address of float in addrspace(0), Offsets={0}, widest fixup type: float*
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; reg(%arr) + 4*reg({%start,+,1}<nsw><%for.body>) + imm(28)
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;
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; to:
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;
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; The chosen solution requires 1 instruction 2 regs, with addrec cost 1, plus 1 scale cost, plus 1 setup cost:
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; LSR Use: Kind=ICmpZero, Offsets={0}, widest fixup type: i64
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; reg({%start,+,1}<nsw><%for.body>)
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; LSR Use: Kind=Basic, Offsets={0}, widest fixup type: i64
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; reg({%start,+,1}<nsw><%for.body>)
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; LSR Use: Kind=Address of float in addrspace(0), Offsets={0}, widest fixup type: float*
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; reg((88888 + %arr)) + 4*reg({%start,+,1}<nsw><%for.body>)
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; float test(float *arr, long long start, float threshold) {
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; for (long long i = start; i != 0; ++i) {
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; float x = arr[i + 7];
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; if (x > threshold)
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; return x;
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; }
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; return -7;
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; }
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define float @test1(float* nocapture readonly %arr, i64 %start, float %threshold) {
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; CHECK-LABEL: test1:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fmov s2, #-7.00000000
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; CHECK-NEXT: cbz x1, .LBB0_5
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; CHECK-NEXT: // %bb.1: // %for.body.preheader
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; CHECK-NEXT: add x8, x1, #7 // =7
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; CHECK-NEXT: .LBB0_2: // %for.body
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: ldr s1, [x0, x8, lsl #2]
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; CHECK-NEXT: fcmp s1, s0
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; CHECK-NEXT: b.gt .LBB0_6
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; CHECK-NEXT: // %bb.3: // %for.cond
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; CHECK-NEXT: // in Loop: Header=BB0_2 Depth=1
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; CHECK-NEXT: add x8, x8, #1 // =1
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; CHECK-NEXT: cmp x8, #7 // =7
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; CHECK-NEXT: b.ne .LBB0_2
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; CHECK-NEXT: // %bb.4:
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB0_5:
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB0_6: // %cleanup2
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; CHECK-NEXT: mov v0.16b, v1.16b
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; CHECK-NEXT: ret
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entry:
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%cmp11 = icmp eq i64 %start, 0
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br i1 %cmp11, label %cleanup2, label %for.body
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for.cond: ; preds = %for.body
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%cmp = icmp eq i64 %inc, 0
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br i1 %cmp, label %cleanup2, label %for.body
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for.body: ; preds = %entry, %for.cond
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%i.012 = phi i64 [ %inc, %for.cond ], [ %start, %entry ]
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%add = add nsw i64 %i.012, 7
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%arrayidx = getelementptr inbounds float, float* %arr, i64 %add
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%0 = load float, float* %arrayidx, align 4
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%cmp1 = fcmp ogt float %0, %threshold
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%inc = add nsw i64 %i.012, 1
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br i1 %cmp1, label %cleanup2, label %for.cond
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cleanup2: ; preds = %for.cond, %for.body, %entry
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%1 = phi float [ -7.000000e+00, %entry ], [ %0, %for.body ], [ -7.000000e+00, %for.cond ]
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ret float %1
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}
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; Same as test1, except i has another use:
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; if (x > threshold) ---> if (x > threshold + i)
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define float @test2(float* nocapture readonly %arr, i64 %start, float %threshold) {
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; CHECK-LABEL: test2:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fmov s2, #-7.00000000
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; CHECK-NEXT: cbz x1, .LBB1_4
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; CHECK-NEXT: .LBB1_1: // %for.body
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; CHECK-NEXT: // =>This Inner Loop Header: Depth=1
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; CHECK-NEXT: add x8, x0, x1, lsl #2
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; CHECK-NEXT: ldr s1, [x8, #28]
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; CHECK-NEXT: scvtf s3, x1
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; CHECK-NEXT: fadd s3, s3, s0
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; CHECK-NEXT: fcmp s1, s3
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; CHECK-NEXT: b.gt .LBB1_5
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; CHECK-NEXT: // %bb.2: // %for.cond
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; CHECK-NEXT: // in Loop: Header=BB1_1 Depth=1
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; CHECK-NEXT: add x1, x1, #1 // =1
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; CHECK-NEXT: cbnz x1, .LBB1_1
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; CHECK-NEXT: // %bb.3:
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB1_4:
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB1_5: // %cleanup4
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; CHECK-NEXT: mov v0.16b, v1.16b
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; CHECK-NEXT: ret
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entry:
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%cmp14 = icmp eq i64 %start, 0
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br i1 %cmp14, label %cleanup4, label %for.body
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for.cond: ; preds = %for.body
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%cmp = icmp eq i64 %inc, 0
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br i1 %cmp, label %cleanup4, label %for.body
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for.body: ; preds = %entry, %for.cond
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%i.015 = phi i64 [ %inc, %for.cond ], [ %start, %entry ]
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%add = add nsw i64 %i.015, 7
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%arrayidx = getelementptr inbounds float, float* %arr, i64 %add
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%0 = load float, float* %arrayidx, align 4
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%conv = sitofp i64 %i.015 to float
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%add1 = fadd float %conv, %threshold
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%cmp2 = fcmp ogt float %0, %add1
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%inc = add nsw i64 %i.015, 1
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br i1 %cmp2, label %cleanup4, label %for.cond
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cleanup4: ; preds = %for.cond, %for.body, %entry
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%1 = phi float [ -7.000000e+00, %entry ], [ %0, %for.body ], [ -7.000000e+00, %for.cond ]
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ret float %1
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}
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