733c7fc55d
Since PTX has grown a <2 x half> datatype vectorization has become more important. The late LoadStoreVectorizer intentionally only does loads and stores, but now arithmetic has to be vectorized for optimal throughput too. This is still very limited, SLP vectorization happily creates <2 x half> if it's a legal type but there's still a lot of register moving happening to get that fed into a vectorized store. Overall it's a small performance win by reducing the amount of arithmetic instructions. I haven't really checked what the loop vectorizer does to PTX code, the cost model there might need some more tweaks. I didn't see it causing harm though. Differential Revision: https://reviews.llvm.org/D46130 llvm-svn: 331035
41 lines
1.6 KiB
LLVM
41 lines
1.6 KiB
LLVM
; RUN: opt < %s -basicaa -slp-vectorizer -S -mtriple=nvptx64-nvidia-cuda -mcpu=sm_70 | FileCheck %s
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; RUN: opt < %s -basicaa -slp-vectorizer -S -mtriple=nvptx64-nvidia-cuda -mcpu=sm_40 | FileCheck %s -check-prefix=NOVECTOR
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; CHECK-LABEL: @fusion
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; CHECK: load <2 x half>, <2 x half>*
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; CHECK: fmul fast <2 x half>
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; CHECK: fadd fast <2 x half>
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; CHECK: store <2 x half> %4, <2 x half>
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; NOVECTOR-LABEL: @fusion
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; NOVECTOR: load half
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; NOVECTOR: fmul fast half
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; NOVECTOR: fadd fast half
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; NOVECTOR: fmul fast half
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; NOVECTOR: fadd fast half
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; NOVECTOR: store half
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define void @fusion(i8* noalias nocapture align 256 dereferenceable(19267584) %arg, i8* noalias nocapture readonly align 256 dereferenceable(19267584) %arg1, i32 %arg2, i32 %arg3) local_unnamed_addr #0 {
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%tmp = shl nuw nsw i32 %arg2, 6
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%tmp4 = or i32 %tmp, %arg3
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%tmp5 = shl nuw nsw i32 %tmp4, 2
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%tmp6 = zext i32 %tmp5 to i64
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%tmp7 = or i64 %tmp6, 1
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%tmp10 = bitcast i8* %arg1 to half*
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%tmp11 = getelementptr inbounds half, half* %tmp10, i64 %tmp6
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%tmp12 = load half, half* %tmp11, align 8
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%tmp13 = fmul fast half %tmp12, 0xH5380
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%tmp14 = fadd fast half %tmp13, 0xH57F0
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%tmp15 = bitcast i8* %arg to half*
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%tmp16 = getelementptr inbounds half, half* %tmp15, i64 %tmp6
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store half %tmp14, half* %tmp16, align 8
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%tmp17 = getelementptr inbounds half, half* %tmp10, i64 %tmp7
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%tmp18 = load half, half* %tmp17, align 2
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%tmp19 = fmul fast half %tmp18, 0xH5380
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%tmp20 = fadd fast half %tmp19, 0xH57F0
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%tmp21 = getelementptr inbounds half, half* %tmp15, i64 %tmp7
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store half %tmp20, half* %tmp21, align 2
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ret void
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}
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attributes #0 = { nounwind }
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