fb3d9e1449
A ReadAdvance was incorrectly added to the SchedReadWrite list associated with the following SSE instructions: sqrtss sqrtsd rsqrtss rcpss As a consequence, a wrong operand latency was computed for the register operand used as the base address of the folded load operand. This patch removes the wrong ReadAdvance, and updates the llvm-mca test cases. There is still a problem with correctly modeling partial register writes on XMM registers This other problem is currently tracked here: https://bugs.llvm.org/show_bug.cgi?id=38813 Differential Revision: https://reviews.llvm.org/D51542 llvm-svn: 341326