Matt Arsenault c986d476cd AMDGPU: Update reqd-work-group-size optimization for umin intrinsic ...

This code was pattern matching the ID computation expression as it
appears in the library. This was a compare and select, but now that
umin is canonical, we were no longer matching. Update to match the
intrinsic instead.

2022-04-12 20:03:02 -04:00

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AArch64

AArch64/GlobalISel: Remove pointless s1 legalize rules

2022-04-12 16:54:04 -04:00

AMDGPU

AMDGPU: Update reqd-work-group-size optimization for umin intrinsic

2022-04-12 20:03:02 -04:00

ARC

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ARM

GlobalISel: Add memSizeNotByteSizePow2 legality helper

2022-04-11 19:43:37 -04:00

AVR

[AVR] Merge AVRRelaxMemOperations into AVRExpandPseudoInsts

2022-04-11 02:42:13 +00:00

BPF

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CSKY

[CSKY] support select instruction in floating type

2022-04-08 12:38:50 +08:00

DirectX

Add DXILPrepare CodeGen pass

2022-04-05 11:50:07 -05:00

Generic

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Hexagon

Revert "[CodeGen] Place SDNode debug ID declaration under appropriate #if"

2022-04-06 20:32:53 +03:00

Inputs

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Lanai

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LoongArch

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M68k

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Mips

Mips/GlobalISel: Add test for atomic load

2022-04-12 16:54:03 -04:00

MIR

GlobalISel: Verify atomic load/store ordering restriction

2022-04-11 20:12:22 -04:00

MLRegalloc

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MSP430

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NVPTX

[NVPTX][FIX] Allow __nvvm_reflect in the presence of opaque pointers

2022-04-12 16:42:50 -05:00

PowerPC

[PowerPC] Generate tests for 16-byte atomic load/store. NFC.

2022-04-09 16:36:57 +08:00

RISCV

RegAllocGreedy: Roll back successful recolorings on failure

2022-04-12 19:02:48 -04:00

SPARC

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SystemZ

Revert "[CodeGen] Place SDNode debug ID declaration under appropriate #if"

2022-04-06 20:32:53 +03:00

Thumb

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Thumb2

[DAG] SimplifySetCC - relax fold (X^C1) == C2 --> X == C1^C2

2022-04-06 09:18:08 +01:00

VE

Revert "[CodeGen] Place SDNode debug ID declaration under appropriate #if"

2022-04-06 20:32:53 +03:00

WebAssembly

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WinCFGuard

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WinEH

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X86

[DAG] Add non-uniform vector support to (shl (sr[la] exact X, C1), C2) folds

2022-04-12 12:57:56 +01:00

XCore

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