73cea83a6f
When optimising for code size at the expense of performance, it is often worth saving and restoring some of r0-r3, if IPRA will be able to take advantage of them. This doesn't cost any extra code size if we already have a PUSH/POP pair, and increases the number of available registers across any calls to the function. We already have an optimisation which tries fold the subtract/add of the SP into the PUSH/POP by using extra registers, which somewhat conflicts with this. I've made the new optimisation less aggressive in cases where the existing one is likely to trigger, which gives better results than either of these optimisations by themselves. Differential revision: https://reviews.llvm.org/D69936
98 lines
4.0 KiB
C++
98 lines
4.0 KiB
C++
//===- ARMTargetFrameLowering.h - Define frame lowering for ARM -*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_ARM_ARMFRAMELOWERING_H
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#define LLVM_LIB_TARGET_ARM_ARMFRAMELOWERING_H
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/TargetFrameLowering.h"
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#include <vector>
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namespace llvm {
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class ARMSubtarget;
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class CalleeSavedInfo;
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class MachineFunction;
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class ARMFrameLowering : public TargetFrameLowering {
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protected:
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const ARMSubtarget &STI;
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public:
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explicit ARMFrameLowering(const ARMSubtarget &sti);
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/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
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/// the function.
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void emitPrologue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
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void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
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bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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ArrayRef<CalleeSavedInfo> CSI,
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const TargetRegisterInfo *TRI) const override;
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bool
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restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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MutableArrayRef<CalleeSavedInfo> CSI,
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const TargetRegisterInfo *TRI) const override;
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bool keepFramePointer(const MachineFunction &MF) const override;
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bool enableCalleeSaveSkip(const MachineFunction &MF) const override;
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bool hasFP(const MachineFunction &MF) const override;
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bool hasReservedCallFrame(const MachineFunction &MF) const override;
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bool canSimplifyCallFramePseudos(const MachineFunction &MF) const override;
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int getFrameIndexReference(const MachineFunction &MF, int FI,
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unsigned &FrameReg) const override;
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int ResolveFrameIndexReference(const MachineFunction &MF, int FI,
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unsigned &FrameReg, int SPAdj) const;
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void getCalleeSaves(const MachineFunction &MF,
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BitVector &SavedRegs) const override;
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void findRegDefsOutsideSaveRestore(MachineFunction &MF,
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BitVector &Regs) const;
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unsigned spillExtraRegsForIPRA(MachineFunction &MF, BitVector &SavedRegs,
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bool HasFPRegSaves) const;
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void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
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RegScavenger *RS) const override;
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void adjustForSegmentedStacks(MachineFunction &MF,
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MachineBasicBlock &MBB) const override;
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/// Returns true if the target will correctly handle shrink wrapping.
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bool enableShrinkWrapping(const MachineFunction &MF) const override;
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bool isProfitableForNoCSROpt(const Function &F) const override {
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// The no-CSR optimisation is bad for code size on ARM, because we can save
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// many registers with a single PUSH/POP pair.
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return false;
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}
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private:
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void emitPushInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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ArrayRef<CalleeSavedInfo> CSI, unsigned StmOpc,
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unsigned StrOpc, bool NoGap, bool (*Func)(unsigned, bool),
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unsigned NumAlignedDPRCS2Regs, unsigned MIFlags = 0) const;
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void emitPopInst(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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MutableArrayRef<CalleeSavedInfo> CSI, unsigned LdmOpc,
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unsigned LdrOpc, bool isVarArg, bool NoGap,
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bool (*Func)(unsigned, bool),
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unsigned NumAlignedDPRCS2Regs) const;
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MachineBasicBlock::iterator
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eliminateCallFramePseudoInstr(MachineFunction &MF,
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI) const override;
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_ARM_ARMFRAMELOWERING_H
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