bf5c84861c
Added initial support for L2 parallelism in SPMD mode. Note, though, that the orphaned parallel directives are not currently supported in SPMD mode. llvm-svn: 332016
250 lines
9.9 KiB
C++
250 lines
9.9 KiB
C++
// Test target codegen - host bc file has to be created first.
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
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// RUN: %clang_cc1 -verify -fopenmp -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
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// expected-no-diagnostics
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#ifndef HEADER
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#define HEADER
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// Check that the execution mode of all 2 target regions is set to Generic Mode.
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// CHECK-DAG: {{@__omp_offloading_.+l27}}_exec_mode = weak constant i8 1
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// CHECK-DAG: {{@__omp_offloading_.+l32}}_exec_mode = weak constant i8 1
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// CHECK-DAG: {{@__omp_offloading_.+l37}}_exec_mode = weak constant i8 0
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template<typename tx>
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tx ftemplate(int n) {
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tx a = 0;
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short aa = 0;
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tx b[10];
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#pragma omp target teams if(0)
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{
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b[2] += 1;
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}
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#pragma omp target teams if(1)
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{
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a = '1';
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}
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#pragma omp target teams if(n>40)
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{
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aa = 1;
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}
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#pragma omp target teams
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{
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#pragma omp parallel
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#pragma omp parallel
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aa = 1;
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}
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return a;
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}
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int bar(int n){
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int a = 0;
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a += ftemplate<char>(n);
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return a;
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}
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// CHECK-NOT: define {{.*}}void {{@__omp_offloading_.+template.+l22}}_worker()
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// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l27}}_worker()
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// CHECK-DAG: [[OMP_EXEC_STATUS:%.+]] = alloca i8,
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// CHECK-DAG: [[OMP_WORK_FN:%.+]] = alloca i8*,
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// CHECK: store i8* null, i8** [[OMP_WORK_FN]],
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// CHECK: store i8 0, i8* [[OMP_EXEC_STATUS]],
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// CHECK: br label {{%?}}[[AWAIT_WORK:.+]]
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//
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// CHECK: [[AWAIT_WORK]]
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// CHECK: call void @llvm.nvvm.barrier0()
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// CHECK: [[KPR:%.+]] = call i1 @__kmpc_kernel_parallel(i8** [[OMP_WORK_FN]], i16 1)
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// CHECK: [[KPRB:%.+]] = zext i1 [[KPR]] to i8
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// store i8 [[KPRB]], i8* [[OMP_EXEC_STATUS]], align 1
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// CHECK: [[WORK:%.+]] = load i8*, i8** [[OMP_WORK_FN]],
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// CHECK: [[SHOULD_EXIT:%.+]] = icmp eq i8* [[WORK]], null
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// CHECK: br i1 [[SHOULD_EXIT]], label {{%?}}[[EXIT:.+]], label {{%?}}[[SEL_WORKERS:.+]]
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//
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// CHECK: [[SEL_WORKERS]]
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// CHECK: [[ST:%.+]] = load i8, i8* [[OMP_EXEC_STATUS]]
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// CHECK: [[IS_ACTIVE:%.+]] = icmp ne i8 [[ST]], 0
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// CHECK: br i1 [[IS_ACTIVE]], label {{%?}}[[EXEC_PARALLEL:.+]], label {{%?}}[[BAR_PARALLEL:.+]]
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//
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// CHECK: [[EXEC_PARALLEL]]
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// CHECK: br label {{%?}}[[TERM_PARALLEL:.+]]
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//
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// CHECK: [[TERM_PARALLEL]]
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// CHECK: call void @__kmpc_kernel_end_parallel()
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// CHECK: br label {{%?}}[[BAR_PARALLEL]]
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//
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// CHECK: [[BAR_PARALLEL]]
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// CHECK: call void @llvm.nvvm.barrier0()
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// CHECK: br label {{%?}}[[AWAIT_WORK]]
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//
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// CHECK: [[EXIT]]
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// CHECK: ret void
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// CHECK: define {{.*}}void [[T1:@__omp_offloading_.+template.+l27]](i[[SZ:32|64]] [[A:%[^)]+]])
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// CHECK: store i[[SZ]] [[A]], i[[SZ]]* [[A_ADDR:%.+]], align
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// CHECK: [[CONV:%.+]] = bitcast i[[SZ]]* [[A_ADDR]] to i8*
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// CHECK-DAG: [[TID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
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// CHECK-DAG: [[NTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
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// CHECK-DAG: [[WS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
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// CHECK-DAG: [[TH_LIMIT:%.+]] = sub nuw i32 [[NTH]], [[WS]]
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// CHECK: [[IS_WORKER:%.+]] = icmp ult i32 [[TID]], [[TH_LIMIT]]
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// CHECK: br i1 [[IS_WORKER]], label {{%?}}[[WORKER:.+]], label {{%?}}[[CHECK_MASTER:.+]]
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//
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// CHECK: [[WORKER]]
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// CHECK: {{call|invoke}} void [[T1]]_worker()
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// CHECK: br label {{%?}}[[EXIT:.+]]
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//
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// CHECK: [[CHECK_MASTER]]
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// CHECK-DAG: [[CMTID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
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// CHECK-DAG: [[CMNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
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// CHECK-DAG: [[CMWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
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// CHECK: [[IS_MASTER:%.+]] = icmp eq i32 [[CMTID]],
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// CHECK: br i1 [[IS_MASTER]], label {{%?}}[[MASTER:.+]], label {{%?}}[[EXIT]]
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//
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// CHECK: [[MASTER]]
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// CHECK-DAG: [[MNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
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// CHECK-DAG: [[MWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
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// CHECK: [[MTMP1:%.+]] = sub nuw i32 [[MNTH]], [[MWS]]
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// CHECK: call void @__kmpc_kernel_init(i32 [[MTMP1]]
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//
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// CHECK-NOT: kmpc_fork_teams
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// CHECK: [[A_VAL:%.+]] = load i8, i8* [[CONV]], align
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// CHECK: [[ACP:%.+]] = bitcast i[[SZ]]* [[AC:%.+]] to i8*
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// CHECK: store i8 [[A_VAL]], i8* [[ACP]], align
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// CHECK: [[ACV:%.+]] = load i[[SZ]], i[[SZ]]* [[AC]], align
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// CHECK: store i[[SZ]] [[ACV]], i[[SZ]]* [[A_ADDR_T:%.+]], align
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// CHECK: [[CONV2:%.+]] = bitcast i[[SZ]]* [[A_ADDR_T]] to i8*
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// CHECK: store i8 49, i8* [[CONV2]], align
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// CHECK: br label {{%?}}[[TERMINATE:.+]]
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//
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// CHECK: [[TERMINATE]]
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// CHECK: call void @__kmpc_kernel_deinit(
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// CHECK: call void @llvm.nvvm.barrier0()
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// CHECK: br label {{%?}}[[EXIT]]
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//
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// CHECK: [[EXIT]]
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// CHECK: ret void
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// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l32}}_worker()
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// CHECK-DAG: [[OMP_EXEC_STATUS:%.+]] = alloca i8,
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// CHECK-DAG: [[OMP_WORK_FN:%.+]] = alloca i8*,
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// CHECK: store i8* null, i8** [[OMP_WORK_FN]],
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// CHECK: store i8 0, i8* [[OMP_EXEC_STATUS]],
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// CHECK: br label {{%?}}[[AWAIT_WORK:.+]]
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//
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// CHECK: [[AWAIT_WORK]]
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// CHECK: call void @llvm.nvvm.barrier0()
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// CHECK: [[KPR:%.+]] = call i1 @__kmpc_kernel_parallel(i8** [[OMP_WORK_FN]], i16 1)
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// CHECK: [[KPRB:%.+]] = zext i1 [[KPR]] to i8
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// store i8 [[KPRB]], i8* [[OMP_EXEC_STATUS]], align 1
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// CHECK: [[WORK:%.+]] = load i8*, i8** [[OMP_WORK_FN]],
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// CHECK: [[SHOULD_EXIT:%.+]] = icmp eq i8* [[WORK]], null
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// CHECK: br i1 [[SHOULD_EXIT]], label {{%?}}[[EXIT:.+]], label {{%?}}[[SEL_WORKERS:.+]]
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//
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// CHECK: [[SEL_WORKERS]]
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// CHECK: [[ST:%.+]] = load i8, i8* [[OMP_EXEC_STATUS]]
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// CHECK: [[IS_ACTIVE:%.+]] = icmp ne i8 [[ST]], 0
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// CHECK: br i1 [[IS_ACTIVE]], label {{%?}}[[EXEC_PARALLEL:.+]], label {{%?}}[[BAR_PARALLEL:.+]]
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//
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// CHECK: [[EXEC_PARALLEL]]
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// CHECK: br label {{%?}}[[TERM_PARALLEL:.+]]
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//
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// CHECK: [[TERM_PARALLEL]]
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// CHECK: call void @__kmpc_kernel_end_parallel()
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// CHECK: br label {{%?}}[[BAR_PARALLEL]]
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//
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// CHECK: [[BAR_PARALLEL]]
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// CHECK: call void @llvm.nvvm.barrier0()
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// CHECK: br label {{%?}}[[AWAIT_WORK]]
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//
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// CHECK: [[EXIT]]
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// CHECK: ret void
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// CHECK: define {{.*}}void [[T2:@__omp_offloading_.+template.+l32]](i[[SZ:32|64]] [[AA:%[^)]+]])
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// CHECK: store i[[SZ]] [[AA]], i[[SZ]]* [[AA_ADDR:%.+]], align
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// CHECK: [[CONV:%.+]] = bitcast i[[SZ]]* [[AA_ADDR]] to i16*
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// CHECK-DAG: [[TID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
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// CHECK-DAG: [[NTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
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// CHECK-DAG: [[WS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
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// CHECK-DAG: [[TH_LIMIT:%.+]] = sub nuw i32 [[NTH]], [[WS]]
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// CHECK: [[IS_WORKER:%.+]] = icmp ult i32 [[TID]], [[TH_LIMIT]]
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// CHECK: br i1 [[IS_WORKER]], label {{%?}}[[WORKER:.+]], label {{%?}}[[CHECK_MASTER:.+]]
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//
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// CHECK: [[WORKER]]
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// CHECK: {{call|invoke}} void [[T2]]_worker()
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// CHECK: br label {{%?}}[[EXIT:.+]]
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//
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// CHECK: [[CHECK_MASTER]]
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// CHECK-DAG: [[CMTID:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.tid.x()
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// CHECK-DAG: [[CMNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
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// CHECK-DAG: [[CMWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
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// CHECK: [[IS_MASTER:%.+]] = icmp eq i32 [[CMTID]],
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// CHECK: br i1 [[IS_MASTER]], label {{%?}}[[MASTER:.+]], label {{%?}}[[EXIT]]
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//
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// CHECK: [[MASTER]]
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// CHECK-DAG: [[MNTH:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
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// CHECK-DAG: [[MWS:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.warpsize()
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// CHECK: [[MTMP1:%.+]] = sub nuw i32 [[MNTH]], [[MWS]]
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// CHECK: call void @__kmpc_kernel_init(i32 [[MTMP1]]
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//
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// CHECK-NOT: kmpc_fork_teams
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// CHECK: [[AA_VAL:%.+]] = load i16, i16* [[CONV]], align
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// CHECK: [[ACP:%.+]] = bitcast i[[SZ]]* [[AC:%.+]] to i16*
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// CHECK: store i16 [[AA_VAL]], i16* [[ACP]], align
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// CHECK: [[ACV:%.+]] = load i[[SZ]], i[[SZ]]* [[AC]], align
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// CHECK: store i[[SZ]] [[ACV]], i[[SZ]]* [[AA_ADDR_T:%.+]], align
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// CHECK: [[CONV2:%.+]] = bitcast i[[SZ]]* [[AA_ADDR_T]] to i16*
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// CHECK: store i16 1, i16* [[CONV2]], align
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// CHECK: br label {{%?}}[[TERMINATE:.+]]
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//
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// CHECK: [[TERMINATE]]
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// CHECK: call void @__kmpc_kernel_deinit(
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// CHECK: call void @llvm.nvvm.barrier0()
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// CHECK: br label {{%?}}[[EXIT]]
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//
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// CHECK: [[EXIT]]
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// CHECK: ret void
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// CHECK: define weak void @__omp_offloading_{{.*}}ftemplate{{.*}}_l37(
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// CHECK: call void @__kmpc_spmd_kernel_init(
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// CHECK: call i8* @__kmpc_data_sharing_push_stack(
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// CHECK-NOT: call void @__kmpc_serialized_parallel(
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// CHECK: call void [[L0:@.+]](i32* %{{.+}}, i32* %{{.+}}, i16* %{{.*}})
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// CHECK-NOT: call void @__kmpc_end_serialized_parallel(
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// CHECK: call void @__kmpc_data_sharing_pop_stack(
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// CHECK: call void @__kmpc_spmd_kernel_deinit()
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// CHECK: ret
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// CHECK: define internal void [[L0]](i32* noalias %{{.+}}, i32* noalias %{{.+}}, i16* dereferenceable
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// CHECK: call void @__kmpc_serialized_parallel(
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// CHECK: call void [[L1:@.+]](i32* %{{.+}}, i32* %{{.+}}, i16* %{{.+}})
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// CHECK: call void @__kmpc_end_serialized_parallel(
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// CHECK: ret void
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// CHECK: define internal void [[L1]](i32* noalias %{{.+}}, i32* noalias %{{.+}}, i16* dereferenceable
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// CHECK: store i16 1, i16* %
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// CHECK: ret void
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#endif
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