c3f240f7dc
Summary: For MIPS ABIs with 64-bit floating point registers including newabi and O32 with 64-bit floating point registers, just save and restore the 32 floating-point registers as doubles. For O32 MIPS with 32-bit floating-point registers, save and restore the individual floating-point registers as "plain" registers. These registers are encoded as floats rather than doubles, but the DWARF unwinder assumes that floating-point registers are stored as doubles when reading them from memory (via AddressSpace::getDouble()). Treating the registers as "normal" registers instead causes the DWARF unwinder to fetch them from memory as a 32-bit register. This does mean that for O32 with 32-bit floating-point registers unw_get_fpreg() and unw_set_fpreg() do not work. One would have to use unw_get_reg() and unw_set_reg() instead. However, DWARF unwinding works correctly as the DWARF CFI emits records for individual 32-bit floating-point registers even when they are treated as doubles stored in paired registers. If the lack of unw_get/set_fpreg() becomes a pressing need in the future for O32 MIPS we could add in special handling to make it work. Reviewers: sdardis, compnerd Reviewed By: sdardis Differential Revision: https://reviews.llvm.org/D41968 llvm-svn: 332414
124 lines
4.4 KiB
C
124 lines
4.4 KiB
C
//===------------------------- __libunwind_config.h -----------------------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is dual licensed under the MIT and the University of Illinois Open
|
|
// Source Licenses. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef ____LIBUNWIND_CONFIG_H__
|
|
#define ____LIBUNWIND_CONFIG_H__
|
|
|
|
#if defined(__arm__) && !defined(__USING_SJLJ_EXCEPTIONS__) && \
|
|
!defined(__ARM_DWARF_EH__)
|
|
#define _LIBUNWIND_ARM_EHABI
|
|
#endif
|
|
|
|
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_X86 8
|
|
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_X86_64 32
|
|
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_PPC 112
|
|
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_PPC64 116
|
|
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_ARM64 95
|
|
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_ARM 287
|
|
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_OR1K 31
|
|
#define _LIBUNWIND_HIGHEST_DWARF_REGISTER_MIPS 65
|
|
|
|
#if defined(_LIBUNWIND_IS_NATIVE_ONLY)
|
|
# if defined(__i386__)
|
|
# define _LIBUNWIND_TARGET_I386
|
|
# define _LIBUNWIND_CONTEXT_SIZE 8
|
|
# define _LIBUNWIND_CURSOR_SIZE 15
|
|
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_X86
|
|
# elif defined(__x86_64__)
|
|
# define _LIBUNWIND_TARGET_X86_64 1
|
|
# if defined(_WIN64)
|
|
# define _LIBUNWIND_CONTEXT_SIZE 54
|
|
# define _LIBUNWIND_CURSOR_SIZE 66
|
|
# else
|
|
# define _LIBUNWIND_CONTEXT_SIZE 21
|
|
# define _LIBUNWIND_CURSOR_SIZE 33
|
|
# endif
|
|
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_X86_64
|
|
# elif defined(__powerpc64__)
|
|
# define _LIBUNWIND_TARGET_PPC64 1
|
|
# define _LIBUNWIND_CONTEXT_SIZE 167
|
|
# define _LIBUNWIND_CURSOR_SIZE 179
|
|
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_PPC64
|
|
# elif defined(__ppc__)
|
|
# define _LIBUNWIND_TARGET_PPC 1
|
|
# define _LIBUNWIND_CONTEXT_SIZE 117
|
|
# define _LIBUNWIND_CURSOR_SIZE 124
|
|
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_PPC
|
|
# elif defined(__aarch64__)
|
|
# define _LIBUNWIND_TARGET_AARCH64 1
|
|
# define _LIBUNWIND_CONTEXT_SIZE 66
|
|
# define _LIBUNWIND_CURSOR_SIZE 78
|
|
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_ARM64
|
|
# elif defined(__arm__)
|
|
# define _LIBUNWIND_TARGET_ARM 1
|
|
# if defined(__ARM_WMMX)
|
|
# define _LIBUNWIND_CONTEXT_SIZE 61
|
|
# define _LIBUNWIND_CURSOR_SIZE 68
|
|
# else
|
|
# define _LIBUNWIND_CONTEXT_SIZE 42
|
|
# define _LIBUNWIND_CURSOR_SIZE 49
|
|
# endif
|
|
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_ARM
|
|
# elif defined(__or1k__)
|
|
# define _LIBUNWIND_TARGET_OR1K 1
|
|
# define _LIBUNWIND_CONTEXT_SIZE 16
|
|
# define _LIBUNWIND_CURSOR_SIZE 24
|
|
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_OR1K
|
|
# elif defined(__mips__)
|
|
# if defined(_ABIO32) && _MIPS_SIM == _ABIO32
|
|
# define _LIBUNWIND_TARGET_MIPS_O32 1
|
|
# if defined(__mips_hard_float)
|
|
# define _LIBUNWIND_CONTEXT_SIZE 50
|
|
# define _LIBUNWIND_CURSOR_SIZE 57
|
|
# else
|
|
# define _LIBUNWIND_CONTEXT_SIZE 18
|
|
# define _LIBUNWIND_CURSOR_SIZE 24
|
|
# endif
|
|
# elif defined(_ABIN32) && _MIPS_SIM == _ABIN32
|
|
# define _LIBUNWIND_TARGET_MIPS_NEWABI 1
|
|
# if defined(__mips_hard_float)
|
|
# define _LIBUNWIND_CONTEXT_SIZE 67
|
|
# define _LIBUNWIND_CURSOR_SIZE 74
|
|
# else
|
|
# define _LIBUNWIND_CONTEXT_SIZE 35
|
|
# define _LIBUNWIND_CURSOR_SIZE 42
|
|
# endif
|
|
# elif defined(_ABI64) && _MIPS_SIM == _ABI64
|
|
# define _LIBUNWIND_TARGET_MIPS_NEWABI 1
|
|
# if defined(__mips_hard_float)
|
|
# define _LIBUNWIND_CONTEXT_SIZE 67
|
|
# define _LIBUNWIND_CURSOR_SIZE 79
|
|
# else
|
|
# define _LIBUNWIND_CONTEXT_SIZE 35
|
|
# define _LIBUNWIND_CURSOR_SIZE 47
|
|
# endif
|
|
# else
|
|
# error "Unsupported MIPS ABI and/or environment"
|
|
# endif
|
|
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER _LIBUNWIND_HIGHEST_DWARF_REGISTER_MIPS
|
|
# else
|
|
# error "Unsupported architecture."
|
|
# endif
|
|
#else // !_LIBUNWIND_IS_NATIVE_ONLY
|
|
# define _LIBUNWIND_TARGET_I386
|
|
# define _LIBUNWIND_TARGET_X86_64 1
|
|
# define _LIBUNWIND_TARGET_PPC 1
|
|
# define _LIBUNWIND_TARGET_PPC64 1
|
|
# define _LIBUNWIND_TARGET_AARCH64 1
|
|
# define _LIBUNWIND_TARGET_ARM 1
|
|
# define _LIBUNWIND_TARGET_OR1K 1
|
|
# define _LIBUNWIND_TARGET_MIPS_O32 1
|
|
# define _LIBUNWIND_TARGET_MIPS_NEWABI 1
|
|
# define _LIBUNWIND_CONTEXT_SIZE 167
|
|
# define _LIBUNWIND_CURSOR_SIZE 179
|
|
# define _LIBUNWIND_HIGHEST_DWARF_REGISTER 287
|
|
#endif // _LIBUNWIND_IS_NATIVE_ONLY
|
|
|
|
#endif // ____LIBUNWIND_CONFIG_H__
|