6eaad1e539
Summary: I had a case where multiple nested uniform ifs resulted in code that did v_cmp comparisons, combining the results with s_and_b64, s_or_b64 and s_xor_b64 and using the resulting mask in s_cbranch_vccnz, without first ensuring that bits for inactive lanes were clear. There was already code for inserting an "s_and_b64 vcc, exec, vcc" to clear bits for inactive lanes in the case that the branch is instruction selected as s_cbranch_scc1 and is then changed to s_cbranch_vccnz in SIFixSGPRCopies. I have added the same code into SILowerControlFlow for the case that the branch is instruction selected as s_cbranch_vccnz. This de-optimizes the code in some cases where the s_and is not needed, because vcc is the result of a v_cmp, or multiple v_cmp instructions combined by s_and/s_or. We should add a pass to re-optimize those cases. Reviewers: arsenm, kzhuravl Subscribers: wdng, yaxunl, t-tye, llvm-commits, dstuttard, timcorringham, nhaehnle Differential Revision: https://reviews.llvm.org/D41292 llvm-svn: 322119
124 lines
3.6 KiB
LLVM
124 lines
3.6 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -verify-machineinstrs -O0 < %s
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; GCN-LABEL: {{^}}test_loop:
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; GCN: [[LABEL:BB[0-9+]_[0-9]+]]: ; %for.body{{$}}
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; GCN: ds_read_b32
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; GCN: ds_write_b32
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; GCN: s_branch [[LABEL]]
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; GCN: s_endpgm
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define amdgpu_kernel void @test_loop(float addrspace(3)* %ptr, i32 %n) nounwind {
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entry:
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%cmp = icmp eq i32 %n, -1
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br i1 %cmp, label %for.exit, label %for.body
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for.exit:
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ret void
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for.body:
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%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%tmp = add i32 %indvar, 32
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%arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp
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%vecload = load float, float addrspace(3)* %arrayidx, align 4
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%add = fadd float %vecload, 1.0
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store float %add, float addrspace(3)* %arrayidx, align 8
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%inc = add i32 %indvar, 1
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br label %for.body
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}
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; GCN-LABEL: @loop_const_true
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; GCN: [[LABEL:BB[0-9+]_[0-9]+]]:
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; GCN: ds_read_b32
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; GCN: ds_write_b32
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; GCN: s_branch [[LABEL]]
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define amdgpu_kernel void @loop_const_true(float addrspace(3)* %ptr, i32 %n) nounwind {
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entry:
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br label %for.body
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for.exit:
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ret void
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for.body:
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%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%tmp = add i32 %indvar, 32
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%arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp
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%vecload = load float, float addrspace(3)* %arrayidx, align 4
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%add = fadd float %vecload, 1.0
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store float %add, float addrspace(3)* %arrayidx, align 8
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%inc = add i32 %indvar, 1
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br i1 true, label %for.body, label %for.exit
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}
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; GCN-LABEL: {{^}}loop_const_false:
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; GCN-NOT: s_branch
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; GCN: s_endpgm
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define amdgpu_kernel void @loop_const_false(float addrspace(3)* %ptr, i32 %n) nounwind {
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entry:
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br label %for.body
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for.exit:
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ret void
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; XXX - Should there be an S_ENDPGM?
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for.body:
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%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%tmp = add i32 %indvar, 32
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%arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp
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%vecload = load float, float addrspace(3)* %arrayidx, align 4
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%add = fadd float %vecload, 1.0
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store float %add, float addrspace(3)* %arrayidx, align 8
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%inc = add i32 %indvar, 1
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br i1 false, label %for.body, label %for.exit
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}
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; GCN-LABEL: {{^}}loop_const_undef:
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; GCN-NOT: s_branch
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; GCN: s_endpgm
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define amdgpu_kernel void @loop_const_undef(float addrspace(3)* %ptr, i32 %n) nounwind {
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entry:
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br label %for.body
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for.exit:
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ret void
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; XXX - Should there be an s_endpgm?
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for.body:
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%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%tmp = add i32 %indvar, 32
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%arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp
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%vecload = load float, float addrspace(3)* %arrayidx, align 4
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%add = fadd float %vecload, 1.0
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store float %add, float addrspace(3)* %arrayidx, align 8
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%inc = add i32 %indvar, 1
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br i1 undef, label %for.body, label %for.exit
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}
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; GCN-LABEL: {{^}}loop_arg_0:
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; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
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; GCN: v_cmp_eq_u32{{[^,]*}}, 1,
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; GCN: [[LOOPBB:BB[0-9]+_[0-9]+]]
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; GCN: s_add_i32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80
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; GCN: s_add_i32 s{{[0-9]+}}, s{{[0-9]+}}, 4
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; GCN: s_cbranch_vccnz [[LOOPBB]]
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; GCN-NEXT: ; %bb.2
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; GCN-NEXT: s_endpgm
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define amdgpu_kernel void @loop_arg_0(float addrspace(3)* %ptr, i32 %n, i1 %cond) nounwind {
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entry:
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br label %for.body
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for.exit:
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ret void
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for.body:
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%indvar = phi i32 [ %inc, %for.body ], [ 0, %entry ]
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%tmp = add i32 %indvar, 32
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%arrayidx = getelementptr float, float addrspace(3)* %ptr, i32 %tmp
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%vecload = load float, float addrspace(3)* %arrayidx, align 4
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%add = fadd float %vecload, 1.0
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store float %add, float addrspace(3)* %arrayidx, align 8
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%inc = add i32 %indvar, 1
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br i1 %cond, label %for.body, label %for.exit
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}
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