6995e5dae7
This patch adds the necessary infrastructure to convert instructions that take two register operands to those that take a register and immediate if the necessary operand is produced by a load-immediate. Furthermore, it uses this infrastructure to perform such conversions twice - first at MachineSSA and then pre-emit. There are a number of reasons we may end up with opportunities for this transformation, including but not limited to: - X-Form instructions chosen since the exact offset isn't available at ISEL time - Atomic instructions with constant operands (we will add patterns for this in the future) - Tail duplication may duplicate code where one block contains this redundancy - When emitting compare-free code in PPCDAGToDAGISel, we don't handle constant comparands specially Furthermore, this patch moves the initialization of PPCMIPeepholePass so that it can be used for MIR tests. llvm-svn: 320791
52 lines
2.2 KiB
LLVM
52 lines
2.2 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=powerpc64le-unknown-unknown -mcpu=pwr8 \
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; RUN: -ppc-convert-rr-to-ri -verify-machineinstrs | FileCheck %s
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define void @test(i32 zeroext %parts) {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0: # %cond.end.i
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; CHECK-NEXT: cmplwi 0, 3, 1
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; CHECK-NEXT: bnelr+ 0
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; CHECK-NEXT: # %bb.1: # %test2.exit.us.unr-lcssa
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; CHECK-NEXT: ld 3, 0(3)
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; CHECK-NEXT: std 3, 0(3)
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entry:
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br label %cond.end.i
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cond.end.i: ; preds = %entry
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%cmp18.i = icmp eq i32 %parts, 1
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br i1 %cmp18.i, label %while.body.lr.ph.i.us.preheader, label %test3.exit.split
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while.body.lr.ph.i.us.preheader: ; preds = %cond.end.i
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%0 = icmp eq i32 %parts, 1
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br label %for.body.i62.us.preheader
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for.body.i62.us.preheader: ; preds = %while.body.lr.ph.i.us.preheader
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br i1 %0, label %test2.exit.us.unr-lcssa, label %for.body.i62.us.preheader.new
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for.body.i62.us.preheader.new: ; preds = %for.body.i62.us.preheader
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br label %for.body.i62.us
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for.body.i62.us: ; preds = %if.end.i.us.1, %for.body.i62.us.preheader.new
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%niter = phi i64 [ undef, %for.body.i62.us.preheader.new ], [ %niter.nsub.1, %if.end.i.us.1 ]
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%cmp8.i.us.1 = icmp uge i64 undef, 0
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br label %if.end.i.us.1
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test2.exit.us.unr-lcssa: ; preds = %if.end.i.us.1, %for.body.i62.us.preheader
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%c.addr.036.i.us.unr = phi i64 [ 0, %for.body.i62.us.preheader ], [ %c.addr.1.i.us.1, %if.end.i.us.1 ]
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%1 = load i64, i64* undef, align 8
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%tobool.i61.us.epil = icmp eq i64 %c.addr.036.i.us.unr, 0
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%add.neg.i.us.epil.pn = select i1 %tobool.i61.us.epil, i64 %1, i64 0
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%storemerge269 = sub i64 %add.neg.i.us.epil.pn, 0
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store i64 %storemerge269, i64* undef, align 8
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unreachable
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test3.exit.split: ; preds = %cond.end.i
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ret void
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if.end.i.us.1: ; preds = %for.body.i62.us
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%c.addr.1.i.us.1 = zext i1 %cmp8.i.us.1 to i64
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%niter.nsub.1 = add i64 %niter, -2
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%niter.ncmp.1 = icmp eq i64 %niter.nsub.1, 0
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br i1 %niter.ncmp.1, label %test2.exit.us.unr-lcssa, label %for.body.i62.us
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}
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