d20d0648ed
Summary:
D42479 (rL329525) enabled SDIV combine for pow2 non-splat vector
dividers. But when there is a 1 in a vector, the instruction sequence to
be generated involves shifting a value by the number of its bit widths,
which is undefined
(c64f4dbfe3/lib/CodeGen/SelectionDAG/DAGCombiner.cpp (L6000-L6006)).
Especially, in architectures that do not support vector instructions,
each of element in a vector will be computed separately using scalar
operations, and then the resulting value will be undef for '1' values
in a vector.
(All 1's vector is fine; only vectors mixed with 1 and others will be
affected.)
Reviewers: RKSimon, jgravelle-google
Subscribers: jfb, dschuff, sbc100, jgravelle-google, llvm-commits
Differential Revision: https://reviews.llvm.org/D46161
llvm-svn: 331092
23 lines
717 B
LLVM
23 lines
717 B
LLVM
; RUN: llc < %s -asm-verbose=false -fast-isel=false -disable-wasm-fallthrough-return-opt | FileCheck %s
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target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
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target triple = "wasm32-unknown-unknown-elf"
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; Because there is a 1 in the vector, sdiv should not be reduced to shifts.
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; CHECK-LABEL: vector_sdiv:
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; CHECK-DAG: i32.store
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; CHECK-DAG: i32.div_s
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; CHECK-DAG: i32.store
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; CHECK-DAG: i32.div_s
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; CHECK-DAG: i32.store
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; CHECK-DAG: i32.div_s
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; CHECK-DAG: i32.store
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define void @vector_sdiv(<4 x i32>* %x, <4 x i32>* readonly %y) {
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entry:
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%0 = load <4 x i32>, <4 x i32>* %y, align 16
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%div = sdiv <4 x i32> %0, <i32 1, i32 4, i32 2, i32 8>
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store <4 x i32> %div, <4 x i32>* %x, align 16
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ret void
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}
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