f5be3ad7f8
This was introducing unnecessary padding after the explicit arguments, depending on the alignment of the total struct type. Also has the side effect of avoiding creating an extra GEP for the offset from the base kernel argument to the explicit kernel argument offset. llvm-svn: 335999
248 lines
8.4 KiB
LLVM
248 lines
8.4 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA %s
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; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MESA %s
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; GCN-LABEL: {{^}}kernel_implicitarg_ptr_empty:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 0
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; MESA: kernarg_segment_byte_size = 16
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; HSA: s_load_dword s0, s[4:5], 0x0
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define amdgpu_kernel void @kernel_implicitarg_ptr_empty() #0 {
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%load = load volatile i32, i32 addrspace(4)* %cast
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ret void
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}
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; GCN-LABEL: {{^}}opencl_kernel_implicitarg_ptr_empty:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 48
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; MESA: kernarg_segment_byte_size = 16
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; HSA: s_load_dword s0, s[4:5], 0x0
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define amdgpu_kernel void @opencl_kernel_implicitarg_ptr_empty() #1 {
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%load = load volatile i32, i32 addrspace(4)* %cast
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ret void
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}
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; GCN-LABEL: {{^}}kernel_implicitarg_ptr:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 112
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; MESA: kernarg_segment_byte_size = 464
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; HSA: s_load_dword s0, s[4:5], 0x1c
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define amdgpu_kernel void @kernel_implicitarg_ptr([112 x i8]) #0 {
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%load = load volatile i32, i32 addrspace(4)* %cast
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ret void
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}
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; GCN-LABEL: {{^}}opencl_kernel_implicitarg_ptr:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 160
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; MESA: kernarg_segment_byte_size = 464
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; HSA: s_load_dword s0, s[4:5], 0x1c
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define amdgpu_kernel void @opencl_kernel_implicitarg_ptr([112 x i8]) #1 {
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%load = load volatile i32, i32 addrspace(4)* %cast
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ret void
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}
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; GCN-LABEL: {{^}}func_implicitarg_ptr:
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; GCN: s_waitcnt
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; MESA: s_mov_b64 s[8:9], s[6:7]
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; MESA: s_mov_b32 s11, 0xf000
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; MESA: s_mov_b32 s10, -1
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; MESA: buffer_load_dword v0, off, s[8:11], 0
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; HSA: v_mov_b32_e32 v0, s6
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; HSA: v_mov_b32_e32 v1, s7
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; HSA: flat_load_dword v0, v[0:1]
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; GCN-NEXT: s_waitcnt
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; GCN-NEXT: s_setpc_b64
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define void @func_implicitarg_ptr() #0 {
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%load = load volatile i32, i32 addrspace(4)* %cast
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ret void
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}
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; GCN-LABEL: {{^}}opencl_func_implicitarg_ptr:
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; GCN: s_waitcnt
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; MESA: s_mov_b64 s[8:9], s[6:7]
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; MESA: s_mov_b32 s11, 0xf000
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; MESA: s_mov_b32 s10, -1
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; MESA: buffer_load_dword v0, off, s[8:11], 0
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; HSA: v_mov_b32_e32 v0, s6
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; HSA: v_mov_b32_e32 v1, s7
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; HSA: flat_load_dword v0, v[0:1]
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; GCN-NEXT: s_waitcnt
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; GCN-NEXT: s_setpc_b64
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define void @opencl_func_implicitarg_ptr() #0 {
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%load = load volatile i32, i32 addrspace(4)* %cast
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ret void
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}
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; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func_empty:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 0
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; MESA: kernarg_segment_byte_size = 16
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; GCN: s_mov_b64 s[6:7], s[4:5]
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; GCN: s_swappc_b64
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define amdgpu_kernel void @kernel_call_implicitarg_ptr_func_empty() #0 {
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call void @func_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}opencl_kernel_call_implicitarg_ptr_func_empty:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 48
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; MESA: kernarg_segment_byte_size = 16
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; GCN: s_mov_b64 s[6:7], s[4:5]
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; GCN: s_swappc_b64
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define amdgpu_kernel void @opencl_kernel_call_implicitarg_ptr_func_empty() #1 {
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call void @func_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 112
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; MESA: kernarg_segment_byte_size = 464
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; HSA: s_add_u32 s6, s4, 0x70
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; MESA: s_add_u32 s6, s4, 0x1c0
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; GCN: s_addc_u32 s7, s5, 0{{$}}
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; GCN: s_swappc_b64
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define amdgpu_kernel void @kernel_call_implicitarg_ptr_func([112 x i8]) #0 {
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call void @func_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}opencl_kernel_call_implicitarg_ptr_func:
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; GCN: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 160
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; MESA: kernarg_segment_byte_size = 464
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; HSA: s_add_u32 s6, s4, 0x70
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; MESA: s_add_u32 s6, s4, 0x1c0
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; GCN: s_addc_u32 s7, s5, 0{{$}}
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; GCN: s_swappc_b64
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define amdgpu_kernel void @opencl_kernel_call_implicitarg_ptr_func([112 x i8]) #1 {
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call void @func_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}func_call_implicitarg_ptr_func:
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; GCN-NOT: s6
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; GCN-NOT: s7
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; GCN-NOT: s[6:7]
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define void @func_call_implicitarg_ptr_func() #0 {
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call void @func_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}opencl_func_call_implicitarg_ptr_func:
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; GCN-NOT: s6
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; GCN-NOT: s7
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; GCN-NOT: s[6:7]
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define void @opencl_func_call_implicitarg_ptr_func() #0 {
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call void @func_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}func_kernarg_implicitarg_ptr:
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; GCN: s_waitcnt
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; MESA: s_mov_b64 s[12:13], s[6:7]
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; MESA: s_mov_b32 s15, 0xf000
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; MESA: s_mov_b32 s14, -1
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; MESA: buffer_load_dword v0, off, s[12:15], 0
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; HSA: v_mov_b32_e32 v0, s6
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; HSA: v_mov_b32_e32 v1, s7
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; HSA: flat_load_dword v0, v[0:1]
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; MESA: s_mov_b32 s10, s14
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; MESA: s_mov_b32 s11, s15
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; MESA: buffer_load_dword v0, off, s[8:11], 0
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; HSA: v_mov_b32_e32 v0, s8
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; HSA: v_mov_b32_e32 v1, s9
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; HSA: flat_load_dword v0, v[0:1]
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; GCN: s_waitcnt vmcnt(0)
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define void @func_kernarg_implicitarg_ptr() #0 {
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%kernarg.segment.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast.kernarg.segment.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)*
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%cast.implicitarg = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%load0 = load volatile i32, i32 addrspace(4)* %cast.kernarg.segment.ptr
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%load1 = load volatile i32, i32 addrspace(4)* %cast.implicitarg
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ret void
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}
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; GCN-LABEL: {{^}}opencl_func_kernarg_implicitarg_ptr:
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; GCN: s_waitcnt
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; MESA: s_mov_b64 s[12:13], s[6:7]
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; MESA: s_mov_b32 s15, 0xf000
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; MESA: s_mov_b32 s14, -1
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; MESA: buffer_load_dword v0, off, s[12:15], 0
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; HSA: v_mov_b32_e32 v0, s6
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; HSA: v_mov_b32_e32 v1, s7
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; HSA: flat_load_dword v0, v[0:1]
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; MESA: s_mov_b32 s10, s14
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; MESA: s_mov_b32 s11, s15
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; MESA: buffer_load_dword v0, off, s[8:11], 0
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; HSA: v_mov_b32_e32 v0, s8
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; HSA: v_mov_b32_e32 v1, s9
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; HSA: flat_load_dword v0, v[0:1]
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; GCN: s_waitcnt vmcnt(0)
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define void @opencl_func_kernarg_implicitarg_ptr() #0 {
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%kernarg.segment.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast.kernarg.segment.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)*
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%cast.implicitarg = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%load0 = load volatile i32, i32 addrspace(4)* %cast.kernarg.segment.ptr
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%load1 = load volatile i32, i32 addrspace(4)* %cast.implicitarg
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ret void
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}
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; GCN-LABEL: {{^}}kernel_call_kernarg_implicitarg_ptr_func:
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; GCN: s_mov_b64 s[6:7], s[4:5]
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; HSA: s_add_u32 s8, s6, 0x70
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; MESA: s_add_u32 s8, s6, 0x1c0
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; GCN: s_addc_u32 s9, s7, 0
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; GCN: s_swappc_b64
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define amdgpu_kernel void @kernel_call_kernarg_implicitarg_ptr_func([112 x i8]) #0 {
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call void @func_kernarg_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}kernel_implicitarg_no_struct_align_padding:
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; HSA: kernarg_segment_byte_size = 120
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; MESA: kernarg_segment_byte_size = 84
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; GCN: kernarg_segment_alignment = 6
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define amdgpu_kernel void @kernel_implicitarg_no_struct_align_padding(<16 x i32>, i32) #1 {
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%implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
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%cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
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%load = load volatile i32, i32 addrspace(4)* %cast
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ret void
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}
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declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #2
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declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #2
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attributes #0 = { nounwind noinline }
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attributes #1 = { nounwind noinline "amdgpu-implicitarg-num-bytes"="48" }
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attributes #2 = { nounwind readnone speculatable }
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