84f888ca82
Currently for armv6-m and armv8-m.baseline, we emit constant pool code when we use execute-only (XO) in combination with stack guards. XO is a new feature for armv6-m, and this patch is part of a series of patches that substitutes constant pool generation with the tMOVi32imm equivalent. However XO for armv8-m.baseline has been available for about 6 years, and so for armv8-m.baseline this is a bugfix. Reviewed By: simonwallis2, olista01 Differential Revision: https://reviews.llvm.org/D155170
101 lines
3.4 KiB
LLVM
101 lines
3.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
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; RUN: llc < %s -mtriple=thumbv6m | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv6m -mattr=+execute-only | FileCheck %s -check-prefix=V6M
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; RUN: llc < %s -mtriple=thumbv8m.base -mattr=+execute-only | FileCheck %s -check-prefix=V8MBASE
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define dso_local i32 @main() #0 {
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; CHECK-LABEL: main:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: push {r7, lr}
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; CHECK-NEXT: sub sp, #24
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; CHECK-NEXT: movs r0, #0
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; CHECK-NEXT: str r0, [sp, #4]
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; CHECK-NEXT: ldr r0, .LCPI0_0
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; CHECK-NEXT: ldr r0, [r0]
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; CHECK-NEXT: str r0, [sp, #20]
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; CHECK-NEXT: add r0, sp, #8
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; CHECK-NEXT: ldrb r0, [r0]
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; CHECK-NEXT: ldr r1, [sp, #20]
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; CHECK-NEXT: ldr r2, .LCPI0_0
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; CHECK-NEXT: ldr r2, [r2]
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; CHECK-NEXT: cmp r2, r1
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; CHECK-NEXT: bne .LBB0_2
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; CHECK-NEXT: @ %bb.1: @ %entry
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; CHECK-NEXT: add sp, #24
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; CHECK-NEXT: pop {r7, pc}
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; CHECK-NEXT: .LBB0_2: @ %entry
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; CHECK-NEXT: bl __stack_chk_fail
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; CHECK-NEXT: .p2align 2
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; CHECK-NEXT: @ %bb.3:
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; CHECK-NEXT: .LCPI0_0:
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; CHECK-NEXT: .long __stack_chk_guard
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;
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; V6M-LABEL: main:
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; V6M: @ %bb.0: @ %entry
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; V6M-NEXT: push {r7, lr}
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; V6M-NEXT: sub sp, #24
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; V6M-NEXT: movs r0, #0
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; V6M-NEXT: str r0, [sp, #4]
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; V6M-NEXT: movs r0, :upper8_15:__stack_chk_guard
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; V6M-NEXT: lsls r0, r0, #8
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; V6M-NEXT: adds r0, :upper0_7:__stack_chk_guard
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; V6M-NEXT: lsls r0, r0, #8
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; V6M-NEXT: adds r0, :lower8_15:__stack_chk_guard
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; V6M-NEXT: lsls r0, r0, #8
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; V6M-NEXT: adds r0, :lower0_7:__stack_chk_guard
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; V6M-NEXT: ldr r0, [r0]
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; V6M-NEXT: str r0, [sp, #20]
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; V6M-NEXT: add r0, sp, #8
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; V6M-NEXT: ldrb r0, [r0]
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; V6M-NEXT: ldr r1, [sp, #20]
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; V6M-NEXT: movs r2, :upper8_15:__stack_chk_guard
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; V6M-NEXT: lsls r2, r2, #8
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; V6M-NEXT: adds r2, :upper0_7:__stack_chk_guard
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; V6M-NEXT: lsls r2, r2, #8
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; V6M-NEXT: adds r2, :lower8_15:__stack_chk_guard
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; V6M-NEXT: lsls r2, r2, #8
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; V6M-NEXT: adds r2, :lower0_7:__stack_chk_guard
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; V6M-NEXT: ldr r2, [r2]
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; V6M-NEXT: cmp r2, r1
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; V6M-NEXT: bne .LBB0_2
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; V6M-NEXT: @ %bb.1: @ %entry
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; V6M-NEXT: add sp, #24
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; V6M-NEXT: pop {r7, pc}
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; V6M-NEXT: .LBB0_2: @ %entry
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; V6M-NEXT: bl __stack_chk_fail
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;
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; V8MBASE-LABEL: main:
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; V8MBASE: @ %bb.0: @ %entry
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; V8MBASE-NEXT: push {r7, lr}
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; V8MBASE-NEXT: sub sp, #24
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; V8MBASE-NEXT: movs r0, #0
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; V8MBASE-NEXT: str r0, [sp, #4]
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; V8MBASE-NEXT: movw r0, :lower16:__stack_chk_guard
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; V8MBASE-NEXT: movt r0, :upper16:__stack_chk_guard
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; V8MBASE-NEXT: ldr r0, [r0]
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; V8MBASE-NEXT: str r0, [sp, #20]
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; V8MBASE-NEXT: add r0, sp, #8
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; V8MBASE-NEXT: ldrb r0, [r0]
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; V8MBASE-NEXT: ldr r1, [sp, #20]
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; V8MBASE-NEXT: movw r2, :lower16:__stack_chk_guard
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; V8MBASE-NEXT: movt r2, :upper16:__stack_chk_guard
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; V8MBASE-NEXT: ldr r2, [r2]
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; V8MBASE-NEXT: cmp r2, r1
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; V8MBASE-NEXT: bne .LBB0_2
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; V8MBASE-NEXT: @ %bb.1: @ %entry
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; V8MBASE-NEXT: add sp, #24
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; V8MBASE-NEXT: pop {r7, pc}
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; V8MBASE-NEXT: .LBB0_2: @ %entry
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; V8MBASE-NEXT: bl __stack_chk_fail
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entry:
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%retval = alloca i32, align 4
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%buffer = alloca [9 x i8], align 1
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store i32 0, ptr %retval, align 4
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%arrayidx = getelementptr inbounds [9 x i8], ptr %buffer, i32 0, i32 0
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%0 = load i8, ptr %arrayidx, align 1
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%conv = zext i8 %0 to i32
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ret i32 %conv
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}
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attributes #0 = { ssp "stack-protector-buffer-size"="8" }
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