91a2ad182d
Running the ARM instruction emulation test on a big-endian system would fail, since the code doesn't respect endianness properly. In EmulateInstructionARM::TestEmulation, code assumes that an instruction opcode read in from the test file is in target byte order, but it was in fact read in in host byte order. More difficult to fix, the EmulationStateARM structure models the overlapping sregs and dregs by a union in _sd_regs. This only works correctly if the host is a little-endian system. I've removed the union in favor of a simple array containing the 32 sregs, and changed any code accessing dregs to explicitly use the correct two sregs overlaying that dreg in the proper target order. Also, the EmulationStateARM::ReadPseudoMemory and WritePseudoMemory track memory as a map of uint32_t values in host byte order, and implement 64-bit memory accessing by splitting them up into two uint32_t ones. However, callers expect memory contents to be provided in the form of a byte array (in target byte order). This means the uint32_t contents need to be byte-swapped on BE systems, and when splitting up a 64-bit access into two 32-bit ones, byte order has to be respected. Differential Revision: http://reviews.llvm.org/D18984 llvm-svn: 266314
97 lines
2.9 KiB
C++
97 lines
2.9 KiB
C++
//===-- lldb_EmulationStateARM.h --------------------------------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#ifndef lldb_EmulationStateARM_h_
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#define lldb_EmulationStateARM_h_
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#include <map>
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#include "lldb/Core/EmulateInstruction.h"
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#include "lldb/Core/Opcode.h"
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class EmulationStateARM {
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public:
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EmulationStateARM ();
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virtual
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~EmulationStateARM ();
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bool
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StorePseudoRegisterValue (uint32_t reg_num, uint64_t value);
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uint64_t
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ReadPseudoRegisterValue (uint32_t reg_num, bool &success);
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bool
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StoreToPseudoAddress (lldb::addr_t p_address, uint32_t value);
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uint32_t
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ReadFromPseudoAddress (lldb::addr_t p_address, bool &success);
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void
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ClearPseudoRegisters ();
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void
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ClearPseudoMemory ();
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bool
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LoadPseudoRegistersFromFrame (lldb_private::StackFrame &frame);
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bool
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LoadStateFromDictionary (lldb_private::OptionValueDictionary *test_data);
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bool
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CompareState (EmulationStateARM &other_state);
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static size_t
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ReadPseudoMemory (lldb_private::EmulateInstruction *instruction,
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void *baton,
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const lldb_private::EmulateInstruction::Context &context,
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lldb::addr_t addr,
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void *dst,
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size_t length);
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static size_t
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WritePseudoMemory (lldb_private::EmulateInstruction *instruction,
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void *baton,
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const lldb_private::EmulateInstruction::Context &context,
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lldb::addr_t addr,
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const void *dst,
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size_t length);
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static bool
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ReadPseudoRegister (lldb_private::EmulateInstruction *instruction,
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void *baton,
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const lldb_private::RegisterInfo *reg_info,
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lldb_private::RegisterValue ®_value);
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static bool
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WritePseudoRegister (lldb_private::EmulateInstruction *instruction,
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void *baton,
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const lldb_private::EmulateInstruction::Context &context,
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const lldb_private::RegisterInfo *reg_info,
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const lldb_private::RegisterValue ®_value);
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private:
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uint32_t m_gpr[17];
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struct _sd_regs
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{
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uint32_t s_regs[32]; // sregs 0 - 31 & dregs 0 - 15
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uint64_t d_regs[16]; // dregs 16-31
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} m_vfp_regs;
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std::map<lldb::addr_t, uint32_t> m_memory; // Eventually will want to change uint32_t to a data buffer heap type.
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DISALLOW_COPY_AND_ASSIGN (EmulationStateARM);
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};
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#endif // lldb_EmulationStateARM_h_
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