0c1e0026aa
Passes to fix three hardware errata that appear on some LEON processor variants. The instructions FSMULD, FMULS and FDIVS do not work as expected on some LEON processors. This change allows those instructions to be substituted for alternatives instruction sequences that are known to work. These passes only run when selected individually, or as part of a processor defintion. They are not included in general SPARC processor compilations for non-LEON processors or for those LEON processors that do not have these hardware errata. llvm-svn: 273108
414 lines
14 KiB
C++
Executable File
414 lines
14 KiB
C++
Executable File
//===------ LeonPasses.cpp - Define passes specific to LEON ---------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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#include "LeonPasses.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/ISDOpcodes.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/IR/LLVMContext.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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using namespace llvm;
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LEONMachineFunctionPass::LEONMachineFunctionPass(TargetMachine &tm, char& ID) :
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MachineFunctionPass(ID)
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{
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}
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LEONMachineFunctionPass::LEONMachineFunctionPass(char& ID) :
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MachineFunctionPass(ID)
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{
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}
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int LEONMachineFunctionPass::GetRegIndexForOperand(MachineInstr& MI, int OperandIndex)
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{
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if (MI.getNumOperands() > 0) {
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if (OperandIndex == LAST_OPERAND) {
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OperandIndex = MI.getNumOperands() - 1;
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}
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if (MI.getNumOperands() > (unsigned) OperandIndex
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&&
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MI.getOperand(OperandIndex).isReg()) {
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return (int) MI.getOperand(OperandIndex).getReg();
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}
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}
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static int NotFoundIndex = -10;
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// Return a different number each time to avoid any comparisons between the values returned.
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NotFoundIndex -= 10;
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return NotFoundIndex;
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}
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void LEONMachineFunctionPass::clearUsedRegisterList()
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{
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UsedRegisters.clear();
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}
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void LEONMachineFunctionPass::markRegisterUsed(int registerIndex)
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{
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UsedRegisters.push_back(registerIndex);
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}
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//finds a new free FP register
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//checks also the AllocatedRegisters vector
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int LEONMachineFunctionPass::getUnusedFPRegister(MachineRegisterInfo& MRI)
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{
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for (int RegisterIndex = SP::F0 ; RegisterIndex <= SP::F31 ; ++RegisterIndex) {
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if (!MRI.isPhysRegUsed(RegisterIndex) &&
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!(std::find(UsedRegisters.begin(), UsedRegisters.end(), RegisterIndex) != UsedRegisters.end())) {
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return RegisterIndex;
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}
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}
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return -1;
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}
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//*****************************************************************************
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//**** InsertNOPLoad pass
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//*****************************************************************************
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//This pass inserts a NOP after any LD or LDF instruction.
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//
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char InsertNOPLoad::ID = 0;
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InsertNOPLoad::InsertNOPLoad(TargetMachine &tm) :
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LEONMachineFunctionPass(tm, ID)
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{
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}
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bool InsertNOPLoad::runOnMachineFunction(MachineFunction& MF)
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{
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Subtarget = &MF.getSubtarget<SparcSubtarget>();
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const TargetInstrInfo& TII = *Subtarget->getInstrInfo();
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DebugLoc DL = DebugLoc();
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bool Modified = false;
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for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
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MachineBasicBlock &MBB = *MFI;
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for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++ MBBI) {
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MachineInstr &MI = *MBBI;
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unsigned Opcode = MI.getOpcode();
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if (Opcode >= SP::LDDArr && Opcode <= SP::LDrr) {
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//errs() << "Inserting NOP after LD instruction\n";
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
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Modified = true;
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}
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else if (MI.isInlineAsm()) {
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// Look for an inline ld or ldf instruction.
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StringRef AsmString =
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MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName();
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if (AsmString.startswith_lower("ld")) {
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//errs() << "Inserting NOP after LD instruction\n";
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
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Modified = true;
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}
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}
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}
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}
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return Modified;
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}
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//*****************************************************************************
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//**** FixFSMULD pass
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//*****************************************************************************
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//this pass should convert the FSMULD operands to double precision in scratch registers,
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//then calculate the result with the FMULD instruction. Therefore, the pass should replace operations of the form:
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//fsmuld %f20,%f21,%f8
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//with the sequence:
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//fstod %f20,%f0
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//fstod %f21,%f2
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//fmuld %f0,%f2,%f8
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//
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char FixFSMULD::ID = 0;
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FixFSMULD::FixFSMULD(TargetMachine &tm) :
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LEONMachineFunctionPass(tm, ID)
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{
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}
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bool FixFSMULD::runOnMachineFunction(MachineFunction& MF)
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{
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Subtarget = &MF.getSubtarget<SparcSubtarget>();
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const TargetInstrInfo& TII = *Subtarget->getInstrInfo();
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DebugLoc DL = DebugLoc();
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//errs() << "FixFSMULD on function " << MF.getName() << "\n";
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bool Modified = false;
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for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
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MachineBasicBlock &MBB = *MFI;
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for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++ MBBI) {
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MachineInstr &MI = *MBBI;
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unsigned Opcode = MI.getOpcode();
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const int UNASSIGNED_INDEX = -1;
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int Reg1Index = UNASSIGNED_INDEX;
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int Reg2Index = UNASSIGNED_INDEX;
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int Reg3Index = UNASSIGNED_INDEX;
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if (Opcode == SP::FSMULD && MI.getNumOperands() == 3) {
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//errs() << "Detected FSMULD\n";
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//take the registers from fsmuld %f20,%f21,%f8
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Reg1Index = MI.getOperand(0).getReg();
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Reg2Index = MI.getOperand(1).getReg();
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Reg3Index = MI.getOperand(2).getReg();
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}
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else if (MI.isInlineAsm()) {
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std::string AsmString (MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName());
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std::string FMULSOpCoode ("fsmuld");
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std::transform(AsmString.begin(), AsmString.end(), AsmString.begin(), ::tolower);
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if (AsmString.find(FMULSOpCoode) == 0) { // this is an inline FSMULD instruction
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//errs() << "Detected InlineAsm FSMULD\n";
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unsigned StartOp = InlineAsm::MIOp_FirstOperand;
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//extracts the registers from the inline assembly instruction
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for (unsigned i = StartOp, e = MI.getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI.getOperand(i);
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if (MO.isReg()) {
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if (Reg1Index == UNASSIGNED_INDEX) Reg1Index = MO.getReg();
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else if (Reg2Index == UNASSIGNED_INDEX) Reg2Index = MO.getReg();
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else if (Reg3Index == UNASSIGNED_INDEX) Reg3Index = MO.getReg();
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}
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if (Reg3Index != UNASSIGNED_INDEX)
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break;
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}
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}
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}
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if (Reg1Index != UNASSIGNED_INDEX && Reg2Index != UNASSIGNED_INDEX && Reg3Index != UNASSIGNED_INDEX) {
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clearUsedRegisterList();
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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//Whatever Reg3Index is hasn't been used yet, so we need to reserve it.
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markRegisterUsed(Reg3Index);
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const int ScratchReg1Index = getUnusedFPRegister(MF.getRegInfo());
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markRegisterUsed(ScratchReg1Index);
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const int ScratchReg2Index = getUnusedFPRegister(MF.getRegInfo());
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markRegisterUsed(ScratchReg2Index);
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if (ScratchReg1Index == UNASSIGNED_INDEX || ScratchReg2Index == UNASSIGNED_INDEX) {
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//errs() << "Cannot allocate free scratch registers for the FixFSMULD pass." << "\n";
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}
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else {
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//create fstod %f20,%f0
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BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD))
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.addReg(ScratchReg1Index)
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.addReg(Reg1Index);
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//create fstod %f21,%f2
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BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD))
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.addReg(ScratchReg2Index)
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.addReg(Reg2Index);
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//create fmuld %f0,%f2,%f8
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BuildMI(MBB, MBBI, DL, TII.get(SP::FMULD))
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.addReg(Reg3Index)
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.addReg(ScratchReg1Index)
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.addReg(ScratchReg2Index);
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MI.eraseFromParent();
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MBBI = NMBBI;
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Modified = true;
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}
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}
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}
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}
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return Modified;
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}
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//*****************************************************************************
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//**** ReplaceFMULS pass
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//*****************************************************************************
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//This pass converts the FMULS operands to double precision in scratch registers,
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//then calculates the result with the FMULD instruction.
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//The pass should replace operations of the form:
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//fmuls %f20,%f21,%f8
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//with the sequence:
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//fstod %f20,%f0
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//fstod %f21,%f2
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//fmuld %f0,%f2,%f8
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//
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char ReplaceFMULS::ID = 0;
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ReplaceFMULS::ReplaceFMULS(TargetMachine &tm) :
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LEONMachineFunctionPass(tm, ID)
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{
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}
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bool ReplaceFMULS::runOnMachineFunction(MachineFunction& MF)
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{
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Subtarget = &MF.getSubtarget<SparcSubtarget>();
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const TargetInstrInfo& TII = *Subtarget->getInstrInfo();
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DebugLoc DL = DebugLoc();
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//errs() << "ReplaceFMULS on function " << MF.getName() << "\n";
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bool Modified = false;
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for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
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MachineBasicBlock &MBB = *MFI;
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for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++ MBBI) {
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MachineInstr &MI = *MBBI;
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unsigned Opcode = MI.getOpcode();
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const int UNASSIGNED_INDEX = -1;
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int Reg1Index = UNASSIGNED_INDEX;
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int Reg2Index = UNASSIGNED_INDEX;
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int Reg3Index = UNASSIGNED_INDEX;
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if (Opcode == SP::FMULS && MI.getNumOperands() == 3) {
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//errs() << "Detected FMULS\n";
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//take the registers from fmuls %f20,%f21,%f8
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Reg1Index = MI.getOperand(0).getReg();
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Reg2Index = MI.getOperand(1).getReg();
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Reg3Index = MI.getOperand(2).getReg();
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}
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else if (MI.isInlineAsm()) {
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std::string AsmString (MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName());
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std::string FMULSOpCoode ("fmuls");
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std::transform(AsmString.begin(), AsmString.end(), AsmString.begin(), ::tolower);
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if (AsmString.find(FMULSOpCoode) == 0) { // this is an inline FMULS instruction
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//errs() << "Detected InlineAsm FMULS\n";
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unsigned StartOp = InlineAsm::MIOp_FirstOperand;
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//extracts the registers from the inline assembly instruction
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for (unsigned i = StartOp, e = MI.getNumOperands(); i != e; ++i) {
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const MachineOperand &MO = MI.getOperand(i);
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if (MO.isReg()) {
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if (Reg1Index == UNASSIGNED_INDEX) Reg1Index = MO.getReg();
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else if (Reg2Index == UNASSIGNED_INDEX) Reg2Index = MO.getReg();
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else if (Reg3Index == UNASSIGNED_INDEX) Reg3Index = MO.getReg();
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}
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if (Reg3Index != UNASSIGNED_INDEX)
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break;
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}
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}
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}
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if (Reg1Index != UNASSIGNED_INDEX && Reg2Index != UNASSIGNED_INDEX && Reg3Index != UNASSIGNED_INDEX) {
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clearUsedRegisterList();
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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//Whatever Reg3Index is hasn't been used yet, so we need to reserve it.
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markRegisterUsed(Reg3Index);
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const int ScratchReg1Index = getUnusedFPRegister(MF.getRegInfo());
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markRegisterUsed(ScratchReg1Index);
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const int ScratchReg2Index = getUnusedFPRegister(MF.getRegInfo());
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markRegisterUsed(ScratchReg2Index);
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if (ScratchReg1Index == UNASSIGNED_INDEX || ScratchReg2Index == UNASSIGNED_INDEX) {
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//errs() << "Cannot allocate free scratch registers for the ReplaceFMULS pass." << "\n";
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}
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else {
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//create fstod %f20,%f0
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BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD))
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.addReg(ScratchReg1Index)
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.addReg(Reg1Index);
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//create fstod %f21,%f2
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BuildMI(MBB, MBBI, DL, TII.get(SP::FSTOD))
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.addReg(ScratchReg2Index)
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.addReg(Reg2Index);
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//create fmuld %f0,%f2,%f8
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BuildMI(MBB, MBBI, DL, TII.get(SP::FMULD))
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.addReg(Reg3Index)
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.addReg(ScratchReg1Index)
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.addReg(ScratchReg2Index);
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MI.eraseFromParent();
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MBBI = NMBBI;
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Modified = true;
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}
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}
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}
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}
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return Modified;
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}
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//*****************************************************************************
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//**** FixAllFDIVSQRT pass
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//*****************************************************************************
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//This pass implements two fixes:
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// 1) fixing the FSQRTS and FSQRTD instructions;
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// 2) fixing the FDIVS and FDIVD instructions.
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//
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char FixAllFDIVSQRT::ID = 0;
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FixAllFDIVSQRT::FixAllFDIVSQRT(TargetMachine &tm) :
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LEONMachineFunctionPass(tm, ID)
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{
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}
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bool FixAllFDIVSQRT::runOnMachineFunction(MachineFunction& MF)
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{
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Subtarget = &MF.getSubtarget<SparcSubtarget>();
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const TargetInstrInfo& TII = *Subtarget->getInstrInfo();
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DebugLoc DL = DebugLoc();
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//errs() << "FixAllFDIVSQRT on function " << MF.getName() << "\n";
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bool Modified = false;
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for (auto MFI = MF.begin(), E = MF.end(); MFI != E; ++MFI) {
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MachineBasicBlock &MBB = *MFI;
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//MBB.print(errs());
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for (auto MBBI = MBB.begin(), E = MBB.end(); MBBI != E; ++ MBBI) {
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MachineInstr &MI = *MBBI;
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//MI.print(errs());
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unsigned Opcode = MI.getOpcode();
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if (MI.isInlineAsm()) {
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std::string AsmString (MI.getOperand(InlineAsm::MIOp_AsmString).getSymbolName());
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std::string FSQRTDOpCode ("fsqrtd");
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std::string FDIVDOpCode ("fdivd");
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std::transform(AsmString.begin(), AsmString.end(), AsmString.begin(), ::tolower);
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if (AsmString.find(FSQRTDOpCode) == 0) { // this is an inline fsqrts instruction
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//errs() << "Detected InlineAsm FSQRTD\n";
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Opcode = SP::FSQRTD;
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}
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else if (AsmString.find(FDIVDOpCode) == 0) { // this is an inline fsqrts instruction
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//errs() << "Detected InlineAsm FDIVD\n";
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Opcode = SP::FDIVD;
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}
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}
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// Note: FDIVS and FSQRTS cannot be generated when this erratum fix is switched on
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// so we don't need to check for them here. They will already have been converted
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// to FSQRTD or FDIVD earlier in the pipeline.
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if (Opcode == SP::FSQRTD || Opcode == SP::FDIVD) {
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//errs() << "Inserting 5 NOPs before FSQRTD,FDIVD.\n";
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for (int InsertedCount=0; InsertedCount<5; InsertedCount++)
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BuildMI(MBB, MBBI, DL, TII.get(SP::NOP));
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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//errs() << "Inserting 28 NOPs after FSQRTD,FDIVD.\n";
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for (int InsertedCount=0; InsertedCount<28; InsertedCount++)
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BuildMI(MBB, NMBBI, DL, TII.get(SP::NOP));
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Modified = true;
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}
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}
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}
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return Modified;
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}
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