4f5b3be7f1
Most immediates are printed in Aarch64InstPrinter using 'formatImm' macro, but not all of them. Implementation contains following rules: - floating point immediates are always printed as decimal - signed integer immediates are printed depends on flag settings (for negative values 'formatImm' macro prints the value as i.e -0x01 which may be convenient when imm is an address or offset) - logical immediates are always printed as hex - the 64-bit immediate for advSIMD, encoded in "a:b:c:d:e:f:g:h" is always printed as hex - the 64-bit immedaite in exception generation instructions like: brk, dcps1, dcps2, dcps3, hlt, hvc, smc, svc is always printed as hex - the rest of immediates is printed depends on availability of -print-imm-hex Signed-off-by: Maciej Gabka <maciej.gabka@arm.com> Signed-off-by: Paul Osmialowski <pawel.osmialowski@arm.com> Differential Revision: http://reviews.llvm.org/D16929 llvm-svn: 269446
89 lines
2.8 KiB
LLVM
89 lines
2.8 KiB
LLVM
; RUN: llc -mtriple=aarch64-eabi %s -o - | FileCheck %s
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; These tests just check that the plumbing is in place for @llvm.bitreverse. The
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; actual output is massive at the moment as llvm.bitreverse is not yet legal.
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declare <2 x i16> @llvm.bitreverse.v2i16(<2 x i16>) readnone
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define <2 x i16> @f(<2 x i16> %a) {
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; CHECK-LABEL: f:
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; CHECK: rev32
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; CHECK: ushr
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%b = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %a)
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ret <2 x i16> %b
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}
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declare i8 @llvm.bitreverse.i8(i8) readnone
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; Unfortunately some of the shift-and-inserts become BFIs, and some do not :(
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define i8 @g(i8 %a) {
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; CHECK-LABEL: g:
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; CHECK-DAG: lsr [[S5:w.*]], w0, #5
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; CHECK-DAG: lsr [[S4:w.*]], w0, #4
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; CHECK-DAG: lsr [[S3:w.*]], w0, #3
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; CHECK-DAG: lsr [[S2:w.*]], w0, #2
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; CHECK-DAG: lsl [[L1:w.*]], w0, #29
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; CHECK-DAG: lsl [[L2:w.*]], w0, #19
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; CHECK-DAG: lsl [[L3:w.*]], w0, #17
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; CHECK-DAG: and [[T1:w.*]], [[L1]], #0x40000000
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; CHECK-DAG: bfi [[T1]], w0, #31, #1
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; CHECK-DAG: bfi [[T1]], [[S2]], #29, #1
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; CHECK-DAG: bfi [[T1]], [[S3]], #28, #1
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; CHECK-DAG: bfi [[T1]], [[S4]], #27, #1
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; CHECK-DAG: bfi [[T1]], [[S5]], #26, #1
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; CHECK-DAG: and [[T2:w.*]], [[L2]], #0x2000000
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; CHECK-DAG: and [[T3:w.*]], [[L3]], #0x1000000
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; CHECK-DAG: orr [[T4:w.*]], [[T1]], [[T2]]
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; CHECK-DAG: orr [[T5:w.*]], [[T4]], [[T3]]
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; CHECK: lsr w0, [[T5]], #24
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%b = call i8 @llvm.bitreverse.i8(i8 %a)
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ret i8 %b
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}
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declare <8 x i8> @llvm.bitreverse.v8i8(<8 x i8>) readnone
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define <8 x i8> @g_vec(<8 x i8> %a) {
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; Try and match as much of the sequence as precisely as possible.
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; CHECK-LABEL: g_vec:
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; CHECK-DAG: movi [[M1:v.*]], #128
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; CHECK-DAG: movi [[M2:v.*]], #64
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; CHECK-DAG: movi [[M3:v.*]], #32
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; CHECK-DAG: movi [[M4:v.*]], #16
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; CHECK-DAG: movi [[M5:v.*]], #8
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; CHECK-DAG: movi [[M6:v.*]], #4{{$}}
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; CHECK-DAG: movi [[M7:v.*]], #2{{$}}
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; CHECK-DAG: movi [[M8:v.*]], #1{{$}}
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; CHECK-DAG: shl [[S1:v.*]], v0.8b, #7
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; CHECK-DAG: shl [[S2:v.*]], v0.8b, #5
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; CHECK-DAG: shl [[S3:v.*]], v0.8b, #3
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; CHECK-DAG: shl [[S4:v.*]], v0.8b, #1
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; CHECK-DAG: ushr [[S5:v.*]], v0.8b, #1
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; CHECK-DAG: ushr [[S6:v.*]], v0.8b, #3
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; CHECK-DAG: ushr [[S7:v.*]], v0.8b, #5
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; CHECK-DAG: ushr [[S8:v.*]], v0.8b, #7
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; CHECK-DAG: and [[A1:v.*]], [[S1]], [[M1]]
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; CHECK-DAG: and [[A2:v.*]], [[S2]], [[M2]]
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; CHECK-DAG: and [[A3:v.*]], [[S3]], [[M3]]
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; CHECK-DAG: and [[A4:v.*]], [[S4]], [[M4]]
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; CHECK-DAG: and [[A5:v.*]], [[S5]], [[M5]]
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; CHECK-DAG: and [[A6:v.*]], [[S6]], [[M6]]
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; CHECK-DAG: and [[A7:v.*]], [[S7]], [[M7]]
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; CHECK-DAG: and [[A8:v.*]], [[S8]], [[M8]]
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; The rest can be ORRed together in any order; it's not worth the test
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; maintenance to match them precisely.
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; CHECK-DAG: orr
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; CHECK-DAG: orr
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; CHECK-DAG: orr
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; CHECK-DAG: orr
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; CHECK-DAG: orr
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; CHECK-DAG: orr
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; CHECK-DAG: orr
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; CHECK: ret
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%b = call <8 x i8> @llvm.bitreverse.v8i8(<8 x i8> %a)
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ret <8 x i8> %b
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}
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