3717aa5ddb
The recent expression type changes still need more discussion, which will happen on phabricator or on the mailing list. The precise list of commits reverted are: - "Refactor division generation code" - "[NFC] Generate runtime checks after the SCoP" - "[FIX] Determine insertion point during SCEV expansion" - "Look through IntToPtr & PtrToInt instructions" - "Use minimal types for generated expressions" - "Temporarily promote values to i64 again" - "[NFC] Avoid unnecessary comparison for min/max expressions" - "[Polly] Fix -Wunused-variable warnings (NFC)" - "[NFC] Simplify min/max expression generation" - "Simplify the type adjustment in the IslExprBuilder" Some of them are just reverted as we would otherwise get conflicts. I will try to re-commit them if possible. llvm-svn: 272483
74 lines
3.0 KiB
LLVM
74 lines
3.0 KiB
LLVM
; RUN: opt %loadPolly -analyze -polly-scops < %s | FileCheck %s
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; RUN: opt %loadPolly -S -polly-codegen -polly-overflow-tracking=never < %s | FileCheck %s --check-prefix=IR
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;
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; As (p + q) can overflow we have to check that we load from
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; I[p + q] only if it does not.
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;
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; CHECK: Invariant Accesses: {
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; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
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; CHECK-NEXT: [N, p, q] -> { Stmt_for_body[i0] -> MemRef_I[p + q] };
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; CHECK-NEXT: Execution Context: [N, p, q] -> { : N > 0 and -2147483648 - p <= q <= 2147483647 - p }
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; CHECK-NEXT: ReadAccess := [Reduction Type: NONE] [Scalar: 0]
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; CHECK-NEXT: [N, p, q] -> { Stmt_for_body[i0] -> MemRef_tmp1[0] };
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; CHECK-NEXT: Execution Context: [N, p, q] -> { : N > 0 }
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; CHECK-NEXT: }
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;
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; IR: polly.preload.merge:
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; IR-NEXT: %polly.preload.tmp1.merge = phi i32* [ %polly.access.I.load, %polly.preload.exec ], [ null, %polly.preload.cond ]
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; IR-NEXT: store i32* %polly.preload.tmp1.merge, i32** %tmp1.preload.s2a
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; IR-NEXT: %12 = sext i32 %N to i64
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; IR-NEXT: %13 = icmp sge i64 %12, 1
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; IR-NEXT: %14 = sext i32 %q to i64
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; IR-NEXT: %15 = sext i32 %p to i64
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; IR-NEXT: %16 = add nsw i64 %15, %14
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; IR-NEXT: %17 = icmp sle i64 %16, 2147483647
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; IR-NEXT: %18 = and i1 %13, %17
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; IR-NEXT: %19 = sext i32 %q to i64
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; IR-NEXT: %20 = sext i32 %p to i64
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; IR-NEXT: %21 = add nsw i64 %20, %19
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; IR-NEXT: %22 = icmp sge i64 %21, -2147483648
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; IR-NEXT: %23 = and i1 %18, %22
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; IR-NEXT: br label %polly.preload.cond1
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;
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; IR: polly.preload.cond1:
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; IR-NEXT: br i1 %23
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;
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; IR: polly.preload.exec3:
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; IR-NEXT: %polly.access.polly.preload.tmp1.merge = getelementptr i32, i32* %polly.preload.tmp1.merge, i64 0
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; IR-NEXT: %polly.access.polly.preload.tmp1.merge.load = load i32, i32* %polly.access.polly.preload.tmp1.merge, align 4
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;
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; void f(int **I, int *A, int N, int p, int q) {
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; for (int i = 0; i < N; i++)
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; A[i] = *(I[p + q]);
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; }
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;
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target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
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define void @f(i32** %I, i32* %A, i32 %N, i32 %p, i32 %q) {
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entry:
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%tmp = sext i32 %N to i64
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br label %for.cond
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for.cond: ; preds = %for.inc, %entry
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%indvars.iv = phi i64 [ %indvars.iv.next, %for.inc ], [ 0, %entry ]
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%cmp = icmp slt i64 %indvars.iv, %tmp
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br i1 %cmp, label %for.body, label %for.end
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for.body: ; preds = %for.cond
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%add = add i32 %p, %q
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%idxprom = sext i32 %add to i64
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%arrayidx = getelementptr inbounds i32*, i32** %I, i64 %idxprom
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%tmp1 = load i32*, i32** %arrayidx, align 8
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%tmp2 = load i32, i32* %tmp1, align 4
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%arrayidx2 = getelementptr inbounds i32, i32* %A, i64 %indvars.iv
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store i32 %tmp2, i32* %arrayidx2, align 4
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br label %for.inc
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for.inc: ; preds = %for.body
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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br label %for.cond
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for.end: ; preds = %for.cond
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ret void
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}
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