cdfd884b0e
Update TableGen specification of DXIL Op records in DXIL.td per the current design document. - Facilitate specification of overloads, shader stage and attributes predicated on DXIL Ops predicated DXIL version. Implement functionality to consume in TableGen backend, DXILEmitter, the above specification enhancements, and generate C++ code (in (DXILOperations.inc) that represents properties of DXIL Ops, associated type declarations and corresponding accessor functions. Changes to DXIL Op Lowering pass to consume the DXIL Op representation generated by the TableGen back end. Add mtriple with the required shader model version to commandline of tests.
666 lines
22 KiB
C++
666 lines
22 KiB
C++
//===- DXILEmitter.cpp - DXIL operation Emitter ---------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// DXILEmitter uses the descriptions of DXIL operation to construct enum and
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// helper functions for DXIL operation.
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//
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//===----------------------------------------------------------------------===//
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#include "Basic/SequenceToOffsetTable.h"
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#include "Common/CodeGenTarget.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/ADT/StringSet.h"
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#include "llvm/CodeGenTypes/MachineValueType.h"
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#include "llvm/Support/DXILABI.h"
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#include "llvm/Support/VersionTuple.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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#include <string>
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#include <vector>
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using namespace llvm;
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using namespace llvm::dxil;
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namespace {
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struct DXILOperationDesc {
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std::string OpName; // name of DXIL operation
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int OpCode; // ID of DXIL operation
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StringRef OpClass; // name of the opcode class
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StringRef Doc; // the documentation description of this instruction
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// Vector of operand type records - return type is at index 0
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SmallVector<Record *> OpTypes;
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SmallVector<Record *> OverloadRecs;
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SmallVector<Record *> StageRecs;
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SmallVector<Record *> AttrRecs;
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StringRef Intrinsic; // The llvm intrinsic map to OpName. Default is "" which
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// means no map exists
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SmallVector<StringRef, 4>
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ShaderStages; // shader stages to which this applies, empty for all.
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int OverloadParamIndex; // Index of parameter with overload type.
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// -1 : no overload types
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SmallVector<StringRef, 4> counters; // counters for this inst.
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DXILOperationDesc(const Record *);
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};
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} // end anonymous namespace
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/// Return dxil::ParameterKind corresponding to input LLVMType record
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///
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/// \param R TableGen def record of class LLVMType
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/// \return ParameterKind As defined in llvm/Support/DXILABI.h
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static ParameterKind getParameterKind(const Record *R) {
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auto VTRec = R->getValueAsDef("VT");
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switch (getValueType(VTRec)) {
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case MVT::isVoid:
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return ParameterKind::Void;
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case MVT::f16:
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return ParameterKind::Half;
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case MVT::f32:
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return ParameterKind::Float;
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case MVT::f64:
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return ParameterKind::Double;
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case MVT::i1:
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return ParameterKind::I1;
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case MVT::i8:
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return ParameterKind::I8;
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case MVT::i16:
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return ParameterKind::I16;
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case MVT::i32:
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return ParameterKind::I32;
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case MVT::fAny:
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case MVT::iAny:
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case MVT::Any:
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return ParameterKind::Overload;
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default:
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llvm_unreachable(
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"Support for specified parameter type not yet implemented");
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}
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}
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/// In-place sort TableGen records of class with a field
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/// Version dxil_version
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/// in the ascending version order.
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static void AscendingSortByVersion(std::vector<Record *> &Recs) {
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std::sort(Recs.begin(), Recs.end(), [](Record *RecA, Record *RecB) {
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unsigned RecAMaj =
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RecA->getValueAsDef("dxil_version")->getValueAsInt("Major");
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unsigned RecAMin =
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RecA->getValueAsDef("dxil_version")->getValueAsInt("Minor");
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unsigned RecBMaj =
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RecB->getValueAsDef("dxil_version")->getValueAsInt("Major");
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unsigned RecBMin =
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RecB->getValueAsDef("dxil_version")->getValueAsInt("Minor");
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return (VersionTuple(RecAMaj, RecAMin) < VersionTuple(RecBMaj, RecBMin));
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});
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}
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/// Construct an object using the DXIL Operation records specified
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/// in DXIL.td. This serves as the single source of reference of
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/// the information extracted from the specified Record R, for
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/// C++ code generated by this TableGen backend.
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// \param R Object representing TableGen record of a DXIL Operation
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DXILOperationDesc::DXILOperationDesc(const Record *R) {
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OpName = R->getNameInitAsString();
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OpCode = R->getValueAsInt("OpCode");
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Doc = R->getValueAsString("Doc");
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SmallVector<Record *> ParamTypeRecs;
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ParamTypeRecs.push_back(R->getValueAsDef("result"));
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std::vector<Record *> ArgTys = R->getValueAsListOfDefs("arguments");
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for (auto Ty : ArgTys) {
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ParamTypeRecs.push_back(Ty);
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}
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size_t ParamTypeRecsSize = ParamTypeRecs.size();
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// Populate OpTypes with return type and parameter types
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// Parameter indices of overloaded parameters.
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// This vector contains overload parameters in the order used to
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// resolve an LLVMMatchType in accordance with convention outlined in
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// the comment before the definition of class LLVMMatchType in
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// llvm/IR/Intrinsics.td
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SmallVector<int> OverloadParamIndices;
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for (unsigned i = 0; i < ParamTypeRecsSize; i++) {
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auto TR = ParamTypeRecs[i];
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// Track operation parameter indices of any overload types
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auto isAny = TR->getValueAsInt("isAny");
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if (isAny == 1) {
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// All overload types in a DXIL Op are required to be of the same type.
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if (!OverloadParamIndices.empty()) {
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bool knownType = true;
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// Ensure that the same overload type registered earlier is being used
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for (auto Idx : OverloadParamIndices) {
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if (TR != ParamTypeRecs[Idx]) {
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knownType = false;
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break;
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}
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}
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assert(knownType && "Specification of multiple differing overload "
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"parameter types not yet supported");
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} else {
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OverloadParamIndices.push_back(i);
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}
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}
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// Populate OpTypes array according to the type specification
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if (TR->isAnonymous()) {
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// Check prior overload types exist
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assert(!OverloadParamIndices.empty() &&
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"No prior overloaded parameter found to match.");
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// Get the parameter index of anonymous type, TR, references
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auto OLParamIndex = TR->getValueAsInt("Number");
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// Resolve and insert the type to that at OLParamIndex
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OpTypes.emplace_back(ParamTypeRecs[OLParamIndex]);
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} else {
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// A non-anonymous type. Just record it in OpTypes
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OpTypes.emplace_back(TR);
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}
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}
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// Set the index of the overload parameter, if any.
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OverloadParamIndex = -1; // default; indicating none
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if (!OverloadParamIndices.empty()) {
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assert(OverloadParamIndices.size() == 1 &&
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"Multiple overload type specification not supported");
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OverloadParamIndex = OverloadParamIndices[0];
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}
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// Get overload records
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std::vector<Record *> Recs = R->getValueAsListOfDefs("overloads");
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// Sort records in ascending order of DXIL version
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AscendingSortByVersion(Recs);
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for (Record *CR : Recs) {
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OverloadRecs.push_back(CR);
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}
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// Get stage records
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Recs = R->getValueAsListOfDefs("stages");
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if (Recs.empty()) {
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PrintFatalError(R, Twine("Atleast one specification of valid stage for ") +
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OpName + " is required");
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}
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// Sort records in ascending order of DXIL version
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AscendingSortByVersion(Recs);
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for (Record *CR : Recs) {
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StageRecs.push_back(CR);
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}
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// Get attribute records
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Recs = R->getValueAsListOfDefs("attributes");
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// Sort records in ascending order of DXIL version
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AscendingSortByVersion(Recs);
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for (Record *CR : Recs) {
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AttrRecs.push_back(CR);
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}
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// Get the operation class
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OpClass = R->getValueAsDef("OpClass")->getName();
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if (!OpClass.str().compare("UnknownOpClass")) {
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PrintFatalError(R, Twine("Unspecified DXIL OpClass for DXIL operation - ") +
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OpName);
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}
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const RecordVal *RV = R->getValue("LLVMIntrinsic");
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if (RV && RV->getValue()) {
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if (DefInit *DI = dyn_cast<DefInit>(RV->getValue())) {
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auto *IntrinsicDef = DI->getDef();
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auto DefName = IntrinsicDef->getName();
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assert(DefName.starts_with("int_") && "invalid intrinsic name");
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// Remove the int_ from intrinsic name.
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Intrinsic = DefName.substr(4);
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}
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}
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}
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/// Return a string representation of ParameterKind enum
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/// \param Kind Parameter Kind enum value
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/// \return std::string string representation of input Kind
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static std::string getParameterKindStr(ParameterKind Kind) {
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switch (Kind) {
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case ParameterKind::Invalid:
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return "Invalid";
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case ParameterKind::Void:
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return "Void";
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case ParameterKind::Half:
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return "Half";
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case ParameterKind::Float:
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return "Float";
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case ParameterKind::Double:
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return "Double";
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case ParameterKind::I1:
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return "I1";
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case ParameterKind::I8:
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return "I8";
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case ParameterKind::I16:
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return "I16";
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case ParameterKind::I32:
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return "I32";
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case ParameterKind::I64:
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return "I64";
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case ParameterKind::Overload:
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return "Overload";
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case ParameterKind::CBufferRet:
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return "CBufferRet";
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case ParameterKind::ResourceRet:
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return "ResourceRet";
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case ParameterKind::DXILHandle:
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return "DXILHandle";
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}
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llvm_unreachable("Unknown llvm::dxil::ParameterKind enum");
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}
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/// Return a string representation of OverloadKind enum that maps to
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/// input LLVMType record
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/// \param R TableGen def record of class LLVMType
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/// \return std::string string representation of OverloadKind
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static std::string getOverloadKindStr(const Record *R) {
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Record *VTRec = R->getValueAsDef("VT");
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switch (getValueType(VTRec)) {
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case MVT::f16:
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return "OverloadKind::HALF";
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case MVT::f32:
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return "OverloadKind::FLOAT";
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case MVT::f64:
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return "OverloadKind::DOUBLE";
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case MVT::i1:
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return "OverloadKind::I1";
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case MVT::i8:
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return "OverloadKind::I8";
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case MVT::i16:
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return "OverloadKind::I16";
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case MVT::i32:
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return "OverloadKind::I32";
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case MVT::i64:
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return "OverloadKind::I64";
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default:
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llvm_unreachable("Support for specified fixed type option for overload "
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"type not supported");
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}
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}
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/// Return a string representation of valid overload information denoted
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// by input records
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//
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/// \param Recs A vector of records of TableGen Overload records
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/// \return std::string string representation of overload mask string
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/// predicated by DXIL Version. E.g.,
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// {{{1, 0}, Mask1}, {{1, 2}, Mask2}, ...}
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static std::string getOverloadMaskString(const SmallVector<Record *> Recs) {
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std::string MaskString = "";
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std::string Prefix = "";
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MaskString.append("{");
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// If no overload information records were specified, assume the operation
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// a) to be supported in DXIL Version 1.0 and later
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// b) has no overload types
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if (Recs.empty()) {
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MaskString.append("{{1, 0}, OverloadKind::UNDEFINED}}");
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} else {
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for (auto Rec : Recs) {
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unsigned Major =
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Rec->getValueAsDef("dxil_version")->getValueAsInt("Major");
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unsigned Minor =
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Rec->getValueAsDef("dxil_version")->getValueAsInt("Minor");
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MaskString.append(Prefix)
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.append("{{")
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.append(std::to_string(Major))
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.append(", ")
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.append(std::to_string(Minor).append("}, "));
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std::string PipePrefix = "";
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auto Tys = Rec->getValueAsListOfDefs("overload_types");
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if (Tys.empty()) {
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MaskString.append("OverloadKind::UNDEFINED");
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}
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for (const auto *Ty : Tys) {
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MaskString.append(PipePrefix).append(getOverloadKindStr(Ty));
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PipePrefix = " | ";
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}
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MaskString.append("}");
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Prefix = ", ";
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}
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MaskString.append("}");
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}
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return MaskString;
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}
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/// Return a string representation of valid shader stag information denoted
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// by input records
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//
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/// \param Recs A vector of records of TableGen Stages records
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/// \return std::string string representation of stages mask string
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/// predicated by DXIL Version. E.g.,
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// {{{1, 0}, Mask1}, {{1, 2}, Mask2}, ...}
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static std::string getStageMaskString(const SmallVector<Record *> Recs) {
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std::string MaskString = "";
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std::string Prefix = "";
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MaskString.append("{");
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// Atleast one stage information record is expected to be specified.
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if (Recs.empty()) {
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PrintFatalError("Atleast one specification of valid stages for "
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"operation must be specified");
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}
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for (auto Rec : Recs) {
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unsigned Major = Rec->getValueAsDef("dxil_version")->getValueAsInt("Major");
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unsigned Minor = Rec->getValueAsDef("dxil_version")->getValueAsInt("Minor");
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MaskString.append(Prefix)
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.append("{{")
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.append(std::to_string(Major))
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.append(", ")
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.append(std::to_string(Minor).append("}, "));
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std::string PipePrefix = "";
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auto Stages = Rec->getValueAsListOfDefs("shader_stages");
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if (Stages.empty()) {
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PrintFatalError("No valid stages for operation specified");
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}
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for (const auto *S : Stages) {
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MaskString.append(PipePrefix).append("ShaderKind::").append(S->getName());
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PipePrefix = " | ";
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}
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MaskString.append("}");
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Prefix = ", ";
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}
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MaskString.append("}");
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return MaskString;
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}
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/// Return a string representation of valid attribute information denoted
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// by input records
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//
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/// \param Recs A vector of records of TableGen Attribute records
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/// \return std::string string representation of stages mask string
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/// predicated by DXIL Version. E.g.,
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// {{{1, 0}, Mask1}, {{1, 2}, Mask2}, ...}
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static std::string getAttributeMaskString(const SmallVector<Record *> Recs) {
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std::string MaskString = "";
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std::string Prefix = "";
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MaskString.append("{");
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for (auto Rec : Recs) {
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unsigned Major = Rec->getValueAsDef("dxil_version")->getValueAsInt("Major");
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unsigned Minor = Rec->getValueAsDef("dxil_version")->getValueAsInt("Minor");
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MaskString.append(Prefix)
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.append("{{")
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.append(std::to_string(Major))
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.append(", ")
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.append(std::to_string(Minor).append("}, "));
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std::string PipePrefix = "";
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auto Attrs = Rec->getValueAsListOfDefs("op_attrs");
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if (Attrs.empty()) {
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MaskString.append("Attribute::None");
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} else {
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for (const auto *Attr : Attrs) {
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MaskString.append(PipePrefix)
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.append("Attribute::")
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.append(Attr->getName());
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PipePrefix = " | ";
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}
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}
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MaskString.append("}");
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Prefix = ", ";
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}
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MaskString.append("}");
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return MaskString;
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}
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/// Emit Enums of DXIL Ops
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/// \param A vector of DXIL Ops
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/// \param Output stream
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static void emitDXILEnums(std::vector<DXILOperationDesc> &Ops,
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raw_ostream &OS) {
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// Sort by OpCode
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llvm::sort(Ops, [](DXILOperationDesc &A, DXILOperationDesc &B) {
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return A.OpCode < B.OpCode;
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});
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OS << "#ifdef DXIL_OP_ENUM\n";
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OS << "// Enumeration for operations specified by DXIL\n";
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OS << "enum class OpCode : unsigned {\n";
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for (auto &Op : Ops) {
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// Name = ID, // Doc
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OS << Op.OpName << " = " << Op.OpCode << ", // " << Op.Doc << "\n";
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}
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OS << "\n};\n\n";
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OS << "// Groups for DXIL operations with equivalent function templates\n";
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OS << "enum class OpCodeClass : unsigned {\n";
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// Build an OpClass set to print
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SmallSet<StringRef, 2> OpClassSet;
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for (auto &Op : Ops) {
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OpClassSet.insert(Op.OpClass);
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}
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for (auto &C : OpClassSet) {
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OS << C << ",\n";
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}
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OS << "\n};\n\n";
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OS << "#endif // DXIL_OP_ENUM\n";
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}
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/// Emit map of DXIL operation to LLVM or DirectX intrinsic
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/// \param A vector of DXIL Ops
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/// \param Output stream
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static void emitDXILIntrinsicMap(std::vector<DXILOperationDesc> &Ops,
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raw_ostream &OS) {
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OS << "\n#ifdef DXIL_OP_INTRINSIC_MAP\n";
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// FIXME: use array instead of SmallDenseMap.
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OS << "static const SmallDenseMap<Intrinsic::ID, dxil::OpCode> LowerMap = "
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"{\n";
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for (auto &Op : Ops) {
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if (Op.Intrinsic.empty())
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continue;
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// {Intrinsic::sin, dxil::OpCode::Sin},
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OS << " { Intrinsic::" << Op.Intrinsic << ", dxil::OpCode::" << Op.OpName
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<< "},\n";
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}
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OS << "};\n\n";
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OS << "#endif // DXIL_OP_INTRINSIC_MAP\n";
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}
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/// Emit DXIL operation table
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/// \param A vector of DXIL Ops
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/// \param Output stream
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static void emitDXILOperationTable(std::vector<DXILOperationDesc> &Ops,
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raw_ostream &OS) {
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// Sort by OpCode.
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llvm::sort(Ops, [](DXILOperationDesc &A, DXILOperationDesc &B) {
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return A.OpCode < B.OpCode;
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});
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// Collect Names.
|
|
SequenceToOffsetTable<std::string> OpClassStrings;
|
|
SequenceToOffsetTable<std::string> OpStrings;
|
|
SequenceToOffsetTable<SmallVector<ParameterKind>> Parameters;
|
|
|
|
StringMap<SmallVector<ParameterKind>> ParameterMap;
|
|
StringSet<> ClassSet;
|
|
for (auto &Op : Ops) {
|
|
OpStrings.add(Op.OpName);
|
|
|
|
if (ClassSet.contains(Op.OpClass))
|
|
continue;
|
|
ClassSet.insert(Op.OpClass);
|
|
OpClassStrings.add(Op.OpClass.data());
|
|
SmallVector<ParameterKind> ParamKindVec;
|
|
// ParamKindVec is a vector of parameters. Skip return type at index 0
|
|
for (unsigned i = 1; i < Op.OpTypes.size(); i++) {
|
|
ParamKindVec.emplace_back(getParameterKind(Op.OpTypes[i]));
|
|
}
|
|
ParameterMap[Op.OpClass] = ParamKindVec;
|
|
Parameters.add(ParamKindVec);
|
|
}
|
|
|
|
// Layout names.
|
|
OpStrings.layout();
|
|
OpClassStrings.layout();
|
|
Parameters.layout();
|
|
|
|
// Emit access function getOpcodeProperty() that embeds DXIL Operation table
|
|
// with entries of type struct OpcodeProperty.
|
|
OS << "static const OpCodeProperty *getOpCodeProperty(dxil::OpCode Op) "
|
|
"{\n";
|
|
|
|
OS << " static const OpCodeProperty OpCodeProps[] = {\n";
|
|
std::string Prefix = "";
|
|
for (auto &Op : Ops) {
|
|
// Consider Op.OverloadParamIndex as the overload parameter index, by
|
|
// default
|
|
auto OLParamIdx = Op.OverloadParamIndex;
|
|
// If no overload parameter index is set, treat first parameter type as
|
|
// overload type - unless the Op has no parameters, in which case treat the
|
|
// return type - as overload parameter to emit the appropriate overload kind
|
|
// enum.
|
|
if (OLParamIdx < 0) {
|
|
OLParamIdx = (Op.OpTypes.size() > 1) ? 1 : 0;
|
|
}
|
|
OS << Prefix << " { dxil::OpCode::" << Op.OpName << ", "
|
|
<< OpStrings.get(Op.OpName) << ", OpCodeClass::" << Op.OpClass << ", "
|
|
<< OpClassStrings.get(Op.OpClass.data()) << ", "
|
|
<< getOverloadMaskString(Op.OverloadRecs) << ", "
|
|
<< getStageMaskString(Op.StageRecs) << ", "
|
|
<< getAttributeMaskString(Op.AttrRecs) << ", " << Op.OverloadParamIndex
|
|
<< ", " << Op.OpTypes.size() - 1 << ", "
|
|
<< Parameters.get(ParameterMap[Op.OpClass]) << " }";
|
|
Prefix = ",\n";
|
|
}
|
|
OS << " };\n";
|
|
|
|
OS << " // FIXME: change search to indexing with\n";
|
|
OS << " // Op once all DXIL operations are added.\n";
|
|
OS << " OpCodeProperty TmpProp;\n";
|
|
OS << " TmpProp.OpCode = Op;\n";
|
|
OS << " const OpCodeProperty *Prop =\n";
|
|
OS << " llvm::lower_bound(OpCodeProps, TmpProp,\n";
|
|
OS << " [](const OpCodeProperty &A, const "
|
|
"OpCodeProperty &B) {\n";
|
|
OS << " return A.OpCode < B.OpCode;\n";
|
|
OS << " });\n";
|
|
OS << " assert(Prop && \"failed to find OpCodeProperty\");\n";
|
|
OS << " return Prop;\n";
|
|
OS << "}\n\n";
|
|
|
|
// Emit the string tables.
|
|
OS << "static const char *getOpCodeName(dxil::OpCode Op) {\n\n";
|
|
|
|
OpStrings.emitStringLiteralDef(OS,
|
|
" static const char DXILOpCodeNameTable[]");
|
|
|
|
OS << " auto *Prop = getOpCodeProperty(Op);\n";
|
|
OS << " unsigned Index = Prop->OpCodeNameOffset;\n";
|
|
OS << " return DXILOpCodeNameTable + Index;\n";
|
|
OS << "}\n\n";
|
|
|
|
OS << "static const char *getOpCodeClassName(const OpCodeProperty &Prop) "
|
|
"{\n\n";
|
|
|
|
OpClassStrings.emitStringLiteralDef(
|
|
OS, " static const char DXILOpCodeClassNameTable[]");
|
|
|
|
OS << " unsigned Index = Prop.OpCodeClassNameOffset;\n";
|
|
OS << " return DXILOpCodeClassNameTable + Index;\n";
|
|
OS << "}\n ";
|
|
|
|
OS << "static const ParameterKind *getOpCodeParameterKind(const "
|
|
"OpCodeProperty &Prop) "
|
|
"{\n\n";
|
|
OS << " static const ParameterKind DXILOpParameterKindTable[] = {\n";
|
|
Parameters.emit(
|
|
OS,
|
|
[](raw_ostream &ParamOS, ParameterKind Kind) {
|
|
ParamOS << "ParameterKind::" << getParameterKindStr(Kind);
|
|
},
|
|
"ParameterKind::Invalid");
|
|
OS << " };\n\n";
|
|
OS << " unsigned Index = Prop.ParameterTableOffset;\n";
|
|
OS << " return DXILOpParameterKindTable + Index;\n";
|
|
OS << "}\n ";
|
|
}
|
|
|
|
static void emitDXILOperationTableDataStructs(RecordKeeper &Records,
|
|
raw_ostream &OS) {
|
|
// Get Shader stage records
|
|
std::vector<Record *> ShaderKindRecs =
|
|
Records.getAllDerivedDefinitions("DXILShaderStage");
|
|
// Sort records by name
|
|
llvm::sort(ShaderKindRecs,
|
|
[](Record *A, Record *B) { return A->getName() < B->getName(); });
|
|
|
|
OS << "// Valid shader kinds\n\n";
|
|
// Choose the type of enum ShaderKind based on the number of stages declared.
|
|
// This gives the flexibility to just add add new stage records in DXIL.td, if
|
|
// needed, with no need to change this backend code.
|
|
size_t ShaderKindCount = ShaderKindRecs.size();
|
|
uint64_t ShaderKindTySz = PowerOf2Ceil(ShaderKindRecs.size() + 1);
|
|
OS << "enum ShaderKind : uint" << ShaderKindTySz << "_t {\n";
|
|
const std::string allStages("all_stages");
|
|
const std::string removed("removed");
|
|
int shiftVal = 1;
|
|
for (auto R : ShaderKindRecs) {
|
|
auto Name = R->getName();
|
|
if (Name.compare(removed) == 0) {
|
|
OS << " " << Name
|
|
<< " = 0, // Pseudo-stage indicating op not supported in any "
|
|
"stage\n";
|
|
} else if (Name.compare(allStages) == 0) {
|
|
OS << " " << Name << " = 0x"
|
|
<< utohexstr(((1 << ShaderKindCount) - 1), false, 0)
|
|
<< ", // Pseudo-stage indicating op is supported in all stages\n";
|
|
} else if (Name.compare(allStages)) {
|
|
OS << " " << Name << " = 1 << " << std::to_string(shiftVal++) << ",\n";
|
|
}
|
|
}
|
|
OS << "}; // enum ShaderKind\n\n";
|
|
}
|
|
|
|
/// Entry function call that invokes the functionality of this TableGen backend
|
|
/// \param Records TableGen records of DXIL Operations defined in DXIL.td
|
|
/// \param OS output stream
|
|
static void EmitDXILOperation(RecordKeeper &Records, raw_ostream &OS) {
|
|
OS << "// Generated code, do not edit.\n";
|
|
OS << "\n";
|
|
// Get all DXIL Ops property records
|
|
std::vector<Record *> OpIntrProps =
|
|
Records.getAllDerivedDefinitions("DXILOp");
|
|
std::vector<DXILOperationDesc> DXILOps;
|
|
for (auto *Record : OpIntrProps) {
|
|
DXILOps.emplace_back(DXILOperationDesc(Record));
|
|
}
|
|
emitDXILEnums(DXILOps, OS);
|
|
emitDXILIntrinsicMap(DXILOps, OS);
|
|
OS << "#ifdef DXIL_OP_OPERATION_TABLE\n";
|
|
emitDXILOperationTableDataStructs(Records, OS);
|
|
emitDXILOperationTable(DXILOps, OS);
|
|
OS << "#endif // DXIL_OP_OPERATION_TABLE\n";
|
|
}
|
|
|
|
static TableGen::Emitter::Opt X("gen-dxil-operation", EmitDXILOperation,
|
|
"Generate DXIL operation information");
|