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clang-p2996/llvm/lib/Target/AMDGPU
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Brox Chen 1eeca67c57 [AMDGPU][True16][MC] validate op_sel and .l/.h syntax (#125872) 
check if op_sel is consistent with .l/.h syntax if both are presented

reopen this https://github.com/llvm/llvm-project/pull/123250 since
problem is resolved in https://github.com/llvm/llvm-project/pull/125561
2025-02-05 13:30:03 -05:00
..
AsmParser
[AMDGPU][True16][MC] validate op_sel and .l/.h syntax (#125872)
2025-02-05 13:30:03 -05:00
Disassembler
[AMDGPU][True16][MC] true16 for v_cmp_lt_f16 (#122499)
2025-01-14 10:03:36 -05:00
MCA
[AMDGPU] Concatenate nested namespaces. NFC.
2024-07-16 15:36:49 +01:00
MCTargetDesc
[AVR] Force relocations for non-encodable jumps (#121498)
2025-01-20 09:23:57 +08:00
TargetInfo
…
Utils
[AMDGPU] Simplify Waitcnt constructor. NFC. (#125672)
2025-02-04 12:09:54 +00:00
AMDGPU.h
[CodeGen][NewPM] Port GCNPreRALongBranchReg to NPM. (#125844)
2025-02-05 18:46:27 +05:30
AMDGPU.td
[AMDGPU] Always emit SI_KILL_I1_PSEUDO for uniform floating point branches. (#124028)
2025-01-29 09:00:40 -08:00
AMDGPUAliasAnalysis.cpp
[AMDGPU] Fix spurious NoAlias results (#122309)
2025-01-20 14:19:30 +00:00
AMDGPUAliasAnalysis.h
[IR] Don't include Module.h in Analysis.h (NFC) (#97023)
2024-06-28 14:30:47 +02:00
AMDGPUAlwaysInlinePass.cpp
…
AMDGPUAnnotateKernelFeatures.cpp
[AMDGPU] Remove unused includes (NFC) (#116154)
2024-11-13 21:10:03 -08:00
AMDGPUAnnotateUniformValues.cpp
[AMDGPU] Preserve all analyses if nothing changed (#117994)
2024-11-28 14:33:05 +00:00
AMDGPUArgumentUsageInfo.cpp
[AMDGPU] Remove unused includes (NFC) (#116154)
2024-11-13 21:10:03 -08:00
AMDGPUArgumentUsageInfo.h
[AMDGPU] Add backward compatibility layer for kernarg preloading (#119167)
2025-01-10 11:39:02 -08:00
AMDGPUAsanInstrumentation.cpp
[IR] Replace of PointerType::get(Type) with opaque version (NFC) (#123617)
2025-01-21 00:32:56 +09:00
AMDGPUAsanInstrumentation.h
[AMDGPU] Update instrumentAddress method to support aligned size and unusual size accesses. (#104804)
2024-08-21 10:31:42 +05:30
AMDGPUAsmPrinter.cpp
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
AMDGPUAsmPrinter.h
[AMDGPU] Convert AMDGPUResourceUsageAnalysis pass from Module to MF pass (#102913)
2024-09-30 11:43:34 +01:00
AMDGPUAtomicOptimizer.cpp
[NFC][DebugInfo] Use iterator moveBefore at many call-sites (#123583)
2025-01-24 10:53:11 +00:00
AMDGPUAttributes.def
Reapply "[AMDGPU] Infer amdgpu-no-flat-scratch-init attribute in AMDGPUAttributor (#94647)" (#118907)
2024-12-09 16:44:48 -08:00
AMDGPUAttributor.cpp
AMDGPU: Fix mishandling of search for constantexpr addrspacecasts (#120346)
2024-12-20 07:37:19 +07:00
AMDGPUCallingConv.td
[NFC][AMDGPU] Use !foreach to replace explicit list of registers (#114005)
2024-10-29 10:50:06 -04:00
AMDGPUCallLowering.cpp
[AMDGPU] Fix hidden kernarg preload count inconsistency (#116759)
2024-12-08 10:10:08 -08:00
AMDGPUCallLowering.h
…
AMDGPUCodeGenPrepare.cpp
[AMDGPU] Rework getDivNumBits API (#119768)
2025-01-09 10:08:13 -05:00
AMDGPUCombine.td
[AMDGPU] [GlobalIsel] Combine Fmul with Select into ldexp instruction. (#120104)
2025-01-06 17:42:38 +05:30
AMDGPUCombinerHelper.cpp
[NFC] Make AMDGPUCombinerHelper methods const (#121903)
2025-01-10 22:43:14 +07:00
AMDGPUCombinerHelper.h
[NFC] Make AMDGPUCombinerHelper methods const (#121903)
2025-01-10 22:43:14 +07:00
AMDGPUCtorDtorLowering.cpp
AMDGPU: Add instruction flags when lowering ctor/dtor (#111652)
2024-10-09 18:03:35 +04:00
AMDGPUCtorDtorLowering.h
…
AMDGPUExportClustering.cpp
…
AMDGPUExportClustering.h
…
AMDGPUFeatures.td
AMDGPU: Increase the LDS size to support to 160 KB for gfx950 (#116309)
2024-11-18 10:48:56 -08:00
AMDGPUFrameLowering.cpp
…
AMDGPUFrameLowering.h
…
AMDGPUGenRegisterBankInfo.def
…
AMDGPUGISel.td
AMDGPU: Add v_permlane16_swap_b32 and v_permlane32_swap_b32 for gfx950 (#117260)
2024-11-22 20:12:50 -08:00
AMDGPUGlobalISelDivergenceLowering.cpp
…
AMDGPUGlobalISelUtils.cpp
[AMDGPU][GlobalISel] Fix assert on APInt creation. (#124608)
2025-01-28 15:53:17 +01:00
AMDGPUGlobalISelUtils.h
AMDGPU/GlobalISel: AMDGPURegBankLegalize (#112864)
2025-01-24 12:12:45 +01:00
AMDGPUHSAMetadataStreamer.cpp
AMDGPU: Treat uint32_max as the default value for amdgpu-max-num-workgroups (#113751)
2024-11-05 12:50:44 -08:00
AMDGPUHSAMetadataStreamer.h
[AMDGPU] MCExpr-ify AMDGPU HSAMetadata (#94788)
2024-06-26 16:39:08 +01:00
AMDGPUIGroupLP.cpp
[AMDGPU] Fix a warning
2025-01-11 13:06:37 -08:00
AMDGPUIGroupLP.h
…
AMDGPUImageIntrinsicOptimizer.cpp
[LLVM] Make more use of IRBuilder::CreateIntrinsic. NFC. (#112706)
2024-10-17 16:20:43 +01:00
AMDGPUInsertDelayAlu.cpp
[AMDGPU] Use the SchedModel available in SIInstrInfo (#110859)
2024-10-02 18:17:27 +02:00
AMDGPUInstCombineIntrinsic.cpp
[AMDGPU] Use correct vector elt type when shrinking mfma scale (#123043)
2025-01-15 14:28:42 +00:00
AMDGPUInstrInfo.cpp
…
AMDGPUInstrInfo.h
…
AMDGPUInstrInfo.td
[AMDGPU] Fix AMDGPUISD::TRAP description (#117453)
2024-11-24 09:25:15 +03:00
AMDGPUInstructions.td
AMDGPU: Define v_mfma_f32_{16x16x128|32x32x64}_f8f6f4 instructions (#116723)
2024-11-21 08:51:58 -08:00
AMDGPUInstructionSelector.cpp
[AMDGPU][True16][CodeGen] true16 codegen for icmp and is_fpclass (#124757)
2025-01-30 12:18:00 -05:00
AMDGPUInstructionSelector.h
AMDGPU/GlobalISel: AMDGPURegBankLegalize (#112864)
2025-01-24 12:12:45 +01:00
AMDGPUISelDAGToDAG.cpp
AMDGPU: Make vector_shuffle legal for v2i32 with v_pk_mov_b32 (#123684)
2025-01-23 20:58:02 +07:00
AMDGPUISelDAGToDAG.h
AMDGPU: Make vector_shuffle legal for v2i32 with v_pk_mov_b32 (#123684)
2025-01-23 20:58:02 +07:00
AMDGPUISelLowering.cpp
AMDGPU: Generalize truncate of shift of cast build_vector combine (#125617)
2025-02-04 11:46:30 +07:00
AMDGPUISelLowering.h
[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)
2024-12-21 05:29:51 +03:00
AMDGPULateCodeGenPrepare.cpp
[AMDGPU] Fix an invalid cast in AMDGPULateCodeGenPrepare::visitLoadInst (#122494)
2025-01-12 23:40:25 -05:00
AMDGPULegalizerInfo.cpp
[CodeGen] Use Register/MCRegister::isPhysical. NFC
2025-01-18 23:37:03 -08:00
AMDGPULegalizerInfo.h
Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (#110714)" v3 (#114443)
2024-11-01 11:13:29 -05:00
AMDGPULibCalls.cpp
AMDGPU: Verify function type matches when matching libcalls (#119043)
2024-12-16 15:01:48 +09:00
AMDGPULibFunc.cpp
[AMDGPU] Provide default value in get intrinsic param type (#122448)
2025-01-10 15:29:42 +01:00
AMDGPULibFunc.h
AMDGPU: Verify function type matches when matching libcalls (#119043)
2024-12-16 15:01:48 +09:00
AMDGPULowerBufferFatPointers.cpp
Reapply "[AMDGPU] Handle natively unsupported types in addrspace(7) lowering" (#123660)
2025-01-20 16:12:17 -06:00
AMDGPULowerKernelArguments.cpp
[AMDGPU] Fix hidden kernarg preload count inconsistency (#116759)
2024-12-08 10:10:08 -08:00
AMDGPULowerKernelAttributes.cpp
AMDGPU: Mark grid size loads with range metadata (#113019)
2024-12-09 11:01:55 -05:00
AMDGPULowerModuleLDSPass.cpp
[AMDGPU] Fix a warning
2024-11-06 12:08:27 -08:00
AMDGPUMachineFunction.cpp
[AMDGPU] Remove unused includes (NFC) (#116154)
2024-11-13 21:10:03 -08:00
AMDGPUMachineFunction.h
Reland "[amdgpu] Add llvm.amdgcn.init.whole.wave intrinsic" (#108512)
2024-09-13 11:54:30 +02:00
AMDGPUMachineModuleInfo.cpp
[AMDGPU] Remove unused includes (NFC) (#116154)
2024-11-13 21:10:03 -08:00
AMDGPUMachineModuleInfo.h
[IR] Remove Function.h include from Analysis.h (NFC) (#97056)
2024-06-28 16:41:00 +02:00
AMDGPUMacroFusion.cpp
…
AMDGPUMacroFusion.h
[CodeGen] Move MISched target hooks into TargetMachine (#125700)
2025-02-05 11:41:37 +05:30
AMDGPUMarkLastScratchLoad.cpp
[CodeGen] Add Register::stackSlotIndex(). Replace uses of Register::stackSlot2Index. NFC (#125028)
2025-01-29 23:02:07 -08:00
AMDGPUMCInstLower.cpp
[AMDGPU] Remove unused includes (NFC) (#116154)
2024-11-13 21:10:03 -08:00
AMDGPUMCInstLower.h
[AMDGPU] Qualify auto. NFC. (#110878)
2024-10-03 13:07:54 +01:00
AMDGPUMCResourceInfo.cpp
[AMDGPU] Change scope of resource usage info symbols (#114810)
2025-01-21 13:10:06 +00:00
AMDGPUMCResourceInfo.h
[AMDGPU] Change scope of resource usage info symbols (#114810)
2025-01-21 13:10:06 +00:00
AMDGPUMemoryUtils.cpp
[llvm][amdgpu] Handle indirect refs to LDS GVs during LDS lowering (#124089)
2025-01-23 14:53:11 +01:00
AMDGPUMemoryUtils.h
[AMDGPU] modify named barrier builtins and intrinsics (#114550)
2024-11-06 10:37:22 -08:00
AMDGPUMIRFormatter.cpp
[AMDGPU] Remove unused includes (NFC) (#116154)
2024-11-13 21:10:03 -08:00
AMDGPUMIRFormatter.h
[AMDGPU] Introduce a pseudo mnemonic for S_DELAY_ALU in MIR. (#96004)
2024-06-20 15:59:08 -04:00
AMDGPUOpenCLEnqueuedBlockLowering.cpp
[AMDGPU][NewPM] Port AMDGPUOpenCLEnqueuedBlockLowering to NPM (#122434)
2025-01-13 17:52:30 +05:30
AMDGPUOpenCLEnqueuedBlockLowering.h
[AMDGPU][NewPM] Port AMDGPUOpenCLEnqueuedBlockLowering to NPM (#122434)
2025-01-13 17:52:30 +05:30
AMDGPUPassRegistry.def
[CodeGen][NewPM] Port GCNPreRALongBranchReg to NPM. (#125844)
2025-02-05 18:46:27 +05:30
AMDGPUPerfHintAnalysis.cpp
[AMDGPU] Qualify auto. NFC. (#110878)
2024-10-03 13:07:54 +01:00
AMDGPUPerfHintAnalysis.h
NewPM/AMDGPU: Port AMDGPUPerfHintAnalysis to new pass manager (#102645)
2024-08-11 15:11:10 +04:00
AMDGPUPostLegalizerCombiner.cpp
[AMDGPU] [GlobalIsel] Combine Fmul with Select into ldexp instruction. (#120104)
2025-01-06 17:42:38 +05:30
AMDGPUPredicateControl.td
…
AMDGPUPreLegalizerCombiner.cpp
[NFC] Make AMDGPUCombinerHelper methods const (#121903)
2025-01-10 22:43:14 +07:00
AMDGPUPreloadKernArgProlog.cpp
[AMDGPU] Add backward compatibility layer for kernarg preloading (#119167)
2025-01-10 11:39:02 -08:00
AMDGPUPreloadKernArgProlog.h
[AMDGPU] Add backward compatibility layer for kernarg preloading (#119167)
2025-01-10 11:39:02 -08:00
AMDGPUPrintfRuntimeBinding.cpp
[IR] Replace of PointerType::get(Type) with opaque version (NFC) (#123617)
2025-01-21 00:32:56 +09:00
AMDGPUPromoteAlloca.cpp
[NFC][AMDGPU] Improve code introduced in #124607 (#124672)
2025-01-27 22:57:16 -05:00
AMDGPUPromoteKernelArguments.cpp
[AMDGPU] Move AMDGPUMemoryUtils out of Utils. NFC. (#104930)
2024-08-20 16:15:46 +01:00
AMDGPUPTNote.h
…
AMDGPURegBankCombiner.cpp
Make CombinerHelper methods const (#119529)
2024-12-20 08:29:18 +07:00
AMDGPURegBankLegalize.cpp
AMDGPU/GlobalISel: AMDGPURegBankLegalize (#112864)
2025-01-24 12:12:45 +01:00
AMDGPURegBankLegalizeHelper.cpp
AMDGPU/GlobalISel: RegBankLegalize rules for load (#112882)
2025-01-24 12:36:41 +01:00
AMDGPURegBankLegalizeHelper.h
AMDGPU/GlobalISel: RegBankLegalize rules for load (#112882)
2025-01-24 12:36:41 +01:00
AMDGPURegBankLegalizeRules.cpp
AMDGPU/GlobalISel: RegBankLegalize rules for load (#112882)
2025-01-24 12:36:41 +01:00
AMDGPURegBankLegalizeRules.h
AMDGPU/GlobalISel: RegBankLegalize rules for load (#112882)
2025-01-24 12:36:41 +01:00
AMDGPURegBankSelect.cpp
AMDGPU/GlobalISel: AMDGPURegBankSelect (#112863)
2025-01-24 11:06:02 +01:00
AMDGPURegisterBankInfo.cpp
[LLVM][AMDGPU] Add Intrinsic and Builtin for ds_bpermute_fi_b32 (#124616)
2025-01-29 14:04:10 +01:00
AMDGPURegisterBankInfo.h
…
AMDGPURegisterBanks.td
…
AMDGPURemoveIncompatibleFunctions.cpp
[AMDGPU][NewPM] Port AMDGPURemoveIncompatibleFunctions to NPM (#122261)
2025-01-13 10:11:40 +05:30
AMDGPURemoveIncompatibleFunctions.h
[AMDGPU][NewPM] Port AMDGPURemoveIncompatibleFunctions to NPM (#122261)
2025-01-13 10:11:40 +05:30
AMDGPUReserveWWMRegs.cpp
[AMDGPU] Remove unused includes (NFC) (#116154)
2024-11-13 21:10:03 -08:00
AMDGPUResourceUsageAnalysis.cpp
[AMDGPU] Remove unused includes (NFC) (#116154)
2024-11-13 21:10:03 -08:00
AMDGPUResourceUsageAnalysis.h
[AMDGPU] Convert AMDGPUResourceUsageAnalysis pass from Module to MF pass (#102913)
2024-09-30 11:43:34 +01:00
AMDGPURewriteOutArguments.cpp
…
AMDGPURewriteUndefForPHI.cpp
…
AMDGPUSearchableTables.td
AMDGPU: Add support for load transpose instructions for gfx950 (#117378)
2024-11-25 09:39:04 -08:00
AMDGPUSelectionDAGInfo.cpp
[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)
2024-12-21 05:29:51 +03:00
AMDGPUSelectionDAGInfo.h
[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)
2024-12-21 05:29:51 +03:00
AMDGPUSetWavePriority.cpp
[AMDGPU] Remove unused includes (NFC) (#116154)
2024-11-13 21:10:03 -08:00
AMDGPUSplitModule.cpp
[AMDGPU] Fix module split's assumption on kernels
2024-12-06 22:56:31 +00:00
AMDGPUSplitModule.h
…
AMDGPUSubtarget.cpp
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
AMDGPUSubtarget.h
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
AMDGPUSwLowerLDS.cpp
[AMDGPU] Remove amdgpu-no-heap-ptr and amdgpu-no-lds-kernel-id attributes from lowered kernels in amdgpu-sw-lower-lds pass (#120887)
2024-12-23 12:42:31 +05:30
AMDGPUTargetMachine.cpp
[CodeGen][NewPM] Port GCNPreRALongBranchReg to NPM. (#125844)
2025-02-05 18:46:27 +05:30
AMDGPUTargetMachine.h
[CodeGen] Move MISched target hooks into TargetMachine (#125700)
2025-02-05 11:41:37 +05:30
AMDGPUTargetObjectFile.cpp
…
AMDGPUTargetObjectFile.h
…
AMDGPUTargetTransformInfo.cpp
[AMDGPU] Remove special cases in TTI::getMemcpyLoop(Residual)LoweringType (#125507)
2025-02-04 08:18:24 +01:00
AMDGPUTargetTransformInfo.h
[KernelInfo] Implement new LLVM IR pass for GPU code analysis (#102944)
2025-01-29 12:40:19 -05:00
AMDGPUUnifyDivergentExitNodes.cpp
[AMDGPU] Remove unused includes (NFC) (#116154)
2024-11-13 21:10:03 -08:00
AMDGPUUnifyDivergentExitNodes.h
…
AMDGPUUnifyMetadata.cpp
[AMDGPU] Qualify auto. NFC. (#110878)
2024-10-03 13:07:54 +01:00
AMDGPUWaitSGPRHazards.cpp
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
AMDGPUWaitSGPRHazards.h
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
AMDKernelCodeT.h
…
BUFInstructions.td
[AMDGPU] Disallow null for more resource operands (#121941)
2025-01-08 08:02:10 +00:00
CaymanInstructions.td
…
CMakeLists.txt
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
DSDIRInstructions.td
[AMDGPU] New GFX12 aliases lds_direct_load and lds_param_load (#119205)
2024-12-09 14:15:56 +00:00
DSInstructions.td
[LLVM][AMDGPU] Add Intrinsic and Builtin for ds_bpermute_fi_b32 (#124616)
2025-01-29 14:04:10 +01:00
EvergreenInstructions.td
…
EXPInstructions.td
…
FLATInstructions.td
[TableGen] Replace WantRoot/WantParent SDNode properties with flags (#119599)
2024-12-12 00:41:44 +03:00
GCNCreateVOPD.cpp
[AMDGPU] Remove unused includes (NFC) (#116154)
2024-11-13 21:10:03 -08:00
GCNDPPCombine.cpp
[AMDGPU] Qualify auto. NFC. (#110878)
2024-10-03 13:07:54 +01:00
GCNDPPCombine.h
[CodeGen][NewPM] Make MFProperties methods const NFC (#113304)
2024-10-25 00:24:44 +05:30
GCNHazardRecognizer.cpp
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
GCNHazardRecognizer.h
[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)
2025-01-30 11:21:11 +09:00
GCNILPSched.cpp
[AMDGPU] Qualify auto. NFC. (#110878)
2024-10-03 13:07:54 +01:00
GCNIterativeScheduler.cpp
[AMDGPU] Optionally Use GCNRPTrackers during scheduling (#93090)
2024-10-09 09:54:11 -07:00
GCNIterativeScheduler.h
…
GCNMinRegStrategy.cpp
[AMDGPU] Qualify auto. NFC. (#110878)
2024-10-03 13:07:54 +01:00
GCNNSAReassign.cpp
[NewPM][CodeGen] Port LiveRegMatrix to NPM (#109938)
2024-10-22 15:28:04 +05:30
GCNPreRALongBranchReg.cpp
[CodeGen][NewPM] Port GCNPreRALongBranchReg to NPM. (#125844)
2025-02-05 18:46:27 +05:30
GCNPreRALongBranchReg.h
[CodeGen][NewPM] Port GCNPreRALongBranchReg to NPM. (#125844)
2025-02-05 18:46:27 +05:30
GCNPreRAOptimizations.cpp
[AMDGPU] Use Lo_32 and Hi_32 helpers (NFC) (#109413)
2024-09-20 14:35:38 +02:00
GCNProcessors.td
AMDGPU: Remove wavefrontsize64 feature from dummy target (#117410)
2024-11-23 09:27:47 -08:00
GCNRegPressure.cpp
[CodeGen] Rename RegisterMaskPair to VRegMaskOrUnit. NFC (#123799)
2025-01-22 09:11:22 -08:00
GCNRegPressure.h
[CodeGen] Rename RegisterMaskPair to VRegMaskOrUnit. NFC (#123799)
2025-01-22 09:11:22 -08:00
GCNRewritePartialRegUses.cpp
[AMDGPU] Remove unused includes (NFC) (#116154)
2024-11-13 21:10:03 -08:00
GCNSchedStrategy.cpp
[AMDGPU] Do not remat instructions with PhysReg uses (#124366)
2025-01-27 10:50:06 -08:00
GCNSchedStrategy.h
[AMDGPU] Add MaxMemoryClauseSchedStrategy (#114957)
2024-12-09 10:07:27 +08:00
GCNSubtarget.cpp
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
GCNSubtarget.h
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
GCNVOPDUtils.cpp
…
GCNVOPDUtils.h
…
InstCombineTables.td
[TableGen] Eliminate static CodeGenIntrinsicMap in PatternParser (#107339)
2024-09-07 15:11:34 -07:00
MIMGInstructions.td
[AMDGPU] Disallow null for more resource operands (#121941)
2025-01-08 08:02:10 +00:00
R600.h
…
R600.td
…
R600AsmPrinter.cpp
…
R600AsmPrinter.h
…
R600ClauseMergePass.cpp
…
R600ControlFlowFinalizer.cpp
[AMDGPU] clang-tidy: no else after return etc. NFC. (#99298)
2024-07-17 21:11:00 +01:00
R600Defines.h
…
R600EmitClauseMarkers.cpp
[AMDGPU] Use range-based for loops (NFC) (#106184)
2024-08-27 06:46:01 -07:00
R600ExpandSpecialInstrs.cpp
…
R600FrameLowering.cpp
…
R600FrameLowering.h
[llvm] Consistently respect naked fn attribute in TargetFrameLowering::hasFP() (#106014)
2024-10-18 09:35:42 +04:00
R600InstrFormats.td
…
R600InstrInfo.cpp
[AMDGPU] Remove unused includes (NFC) (#116154)
2024-11-13 21:10:03 -08:00
R600InstrInfo.h
[TII][RISCV] Add renamable bit to copyPhysReg (#91179)
2024-08-27 10:08:43 +08:00
R600InstrInfo.td
…
R600Instructions.td
…
R600ISelDAGToDAG.cpp
[NFC] Eliminate top-level "using namespace" from some headers. (#102751)
2024-08-11 13:10:48 -07:00
R600ISelLowering.cpp
[IR] Replace of PointerType::get(Type) with opaque version (NFC) (#123617)
2025-01-21 00:32:56 +09:00
R600ISelLowering.h
…
R600MachineCFGStructurizer.cpp
[AMDGPU] clang-tidy: no else after return etc. NFC. (#99298)
2024-07-17 21:11:00 +01:00
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h
…
R600MachineScheduler.cpp
[AMDGPU] Use range-based for loops (NFC) (#106184)
2024-08-27 06:46:01 -07:00
R600MachineScheduler.h
[NFC] Eliminate top-level "using namespace" from some headers. (#102751)
2024-08-11 13:10:48 -07:00
R600MCInstLower.cpp
…
R600OpenCLImageTypeLoweringPass.cpp
[AMDGPU] Qualify auto. NFC. (#110878)
2024-10-03 13:07:54 +01:00
R600OptimizeVectorRegisters.cpp
[AMDGPU] Avoid repeated hash lookups (NFC) (#125632)
2025-02-03 22:40:52 -08:00
R600Packetizer.cpp
[Target] Use range-based for loops (NFC) (#98705)
2024-07-13 17:40:51 -07:00
R600Processors.td
[AMDGPU] Rename LocalMemorySize features to AddressableLocalMemorySize (#110242)
2024-09-30 10:29:31 +01:00
R600RegisterInfo.cpp
…
R600RegisterInfo.h
…
R600RegisterInfo.td
…
R600Schedule.td
…
R600Subtarget.cpp
[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)
2024-12-16 15:13:46 +03:00
R600Subtarget.h
[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)
2024-12-16 15:13:46 +03:00
R600TargetMachine.cpp
[CodeGen] Move MISched target hooks into TargetMachine (#125700)
2025-02-05 11:41:37 +05:30
R600TargetMachine.h
[CodeGen] Move MISched target hooks into TargetMachine (#125700)
2025-02-05 11:41:37 +05:30
R600TargetTransformInfo.cpp
[IR] Add getDataLayout() helpers to Function and GlobalValue (#96919)
2024-06-28 08:36:49 +02:00
R600TargetTransformInfo.h
…
R700Instructions.td
…
SIAnnotateControlFlow.cpp
[NFC][DebugInfo] Make some block-start-position methods return iterators (#124287)
2025-01-27 16:27:54 +00:00
SIDefines.h
AMDGPU: Define v_mfma_f32_{16x16x128|32x32x64}_f8f6f4 instructions (#116723)
2024-11-21 08:51:58 -08:00
SIFixSGPRCopies.cpp
[AMDGPU] Remove unused includes (NFC) (#116154)
2024-11-13 21:10:03 -08:00
SIFixSGPRCopies.h
AMDGPU/NewPM: Port SIFixSGPRCopies to new pass manager (#102614)
2024-08-09 17:52:41 +04:00
SIFixVGPRCopies.cpp
[AMDGPU][NewPM] Port SIFixVGPRCopies to NPM (#123592)
2025-01-21 15:27:46 +05:30
SIFixVGPRCopies.h
[AMDGPU][NewPM] Port SIFixVGPRCopies to NPM (#123592)
2025-01-21 15:27:46 +05:30
SIFoldOperands.cpp
[AMDGPU] Do not fold into v_accvpr_mov/write/read (#120475)
2025-01-07 09:25:01 -06:00
SIFoldOperands.h
AMDGPU/NewPM: Port SIFoldOperands to new pass manager (#105801)
2024-08-29 11:34:54 +05:30
SIFormMemoryClauses.cpp
[CodeGen] Remove unused argument from getCoveringSubRegIndexes. NFC. (#122884)
2025-01-14 12:59:31 +00:00
SIFrameLowering.cpp
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
SIFrameLowering.h
[llvm] Consistently respect naked fn attribute in TargetFrameLowering::hasFP() (#106014)
2024-10-18 09:35:42 +04:00
SIInsertHardClauses.cpp
…
SIInsertWaitcnts.cpp
[AMDGPU] Create new option for force flush load counter (#124974)
2025-01-30 11:14:38 -08:00
SIInstrFormats.td
AMDGPU: Define v_mfma_f32_{16x16x128|32x32x64}_f8f6f4 instructions (#116723)
2024-11-21 08:51:58 -08:00
SIInstrInfo.cpp
[amdgpu][nfc] Post-commit feedback on c39fba209
2025-01-30 20:07:44 +00:00
SIInstrInfo.h
[llvm] Pass MachineInstr flags to storeRegToStackSlot/loadRegFromStackSlot (NFC) (#120622)
2025-01-22 13:36:39 +05:30
SIInstrInfo.td
[AMDGPU] Handle hazard in v_scalef32_sr_fp4_* conversions (#118589)
2024-12-11 18:38:10 +05:30
SIInstructions.td
[AMDGPU][True16][Codegen] true16 codegen for FPtoI1 (#125120)
2025-02-04 11:20:40 -05:00
SIISelLowering.cpp
AMDGPU: Custom lower 32-bit element shuffles (#123711)
2025-01-28 11:17:10 +07:00
SIISelLowering.h
[Mips] Fix compiler crash when returning fp128 after calling a functi… (#117525)
2025-01-20 16:47:40 +08:00
SILateBranchLowering.cpp
Reapply "[DomTreeUpdater] Move critical edge splitting code to updater" (#119547)
2024-12-13 11:43:09 +08:00
SILoadStoreOptimizer.cpp
[AMDGPU] Qualify auto. NFC. (#110878)
2024-10-03 13:07:54 +01:00
SILoadStoreOptimizer.h
[CodeGen][NewPM] Make MFProperties methods const NFC (#113304)
2024-10-25 00:24:44 +05:30
SILowerControlFlow.cpp
[AMDGPU][NewPM] Port SILowerControlFlow pass into NPM. (#123045)
2025-01-16 11:06:38 +05:30
SILowerControlFlow.h
[AMDGPU][NewPM] Port SILowerControlFlow pass into NPM. (#123045)
2025-01-16 11:06:38 +05:30
SILowerI1Copies.cpp
Reapply "[DomTreeUpdater] Move critical edge splitting code to updater" (#119547)
2024-12-13 11:43:09 +08:00
SILowerI1Copies.h
…
SILowerSGPRSpills.cpp
AMDGPU: Delete spills of undef values (#119684)
2024-12-17 13:08:38 +07:00
SILowerSGPRSpills.h
[CodeGen][NewPM] Make MFProperties methods const NFC (#113304)
2024-10-25 00:24:44 +05:30
SILowerWWMCopies.cpp
[AMDGPU][NewPM] Port SILowerWWMCopies to NPM (#123695)
2025-01-22 14:54:01 +05:30
SILowerWWMCopies.h
[AMDGPU][NewPM] Port SILowerWWMCopies to NPM (#123695)
2025-01-22 14:54:01 +05:30
SIMachineFunctionInfo.cpp
[AMDGPU] Occupancy w.r.t. workgroup size range is also a range (#123748)
2025-01-23 16:07:57 +01:00
SIMachineFunctionInfo.h
[AMDGPU] Make max dwords of memory cluster configurable (#119342)
2024-12-18 14:17:27 +08:00
SIMachineScheduler.cpp
[AMDGPU] Replace unsigned with Register in SIMachineScheduler. NFC
2025-01-26 00:26:00 -08:00
SIMachineScheduler.h
[AMDGPU] Replace unsigned with Register in SIMachineScheduler. NFC
2025-01-26 00:26:00 -08:00
SIMemoryLegalizer.cpp
[AMDGPU] Only emit SCOPE_SYS global_wb (#110636)
2024-10-07 07:35:31 +02:00
SIModeRegister.cpp
[AMDGPU][True16][CodeGen] true16 codegen pat for fptrunc_round (#124044)
2025-01-30 18:31:52 -05:00
SIModeRegisterDefaults.cpp
…
SIModeRegisterDefaults.h
…
SIOptimizeExecMasking.cpp
[AMDGPU][NewPM] Port SIOptimizeExecMasking to NPM (#123572)
2025-01-20 16:34:01 +05:30
SIOptimizeExecMasking.h
[AMDGPU][NewPM] Port SIOptimizeExecMasking to NPM (#123572)
2025-01-20 16:34:01 +05:30
SIOptimizeExecMaskingPreRA.cpp
[AMDGPU] Qualify auto. NFC. (#110878)
2024-10-03 13:07:54 +01:00
SIOptimizeVGPRLiveRange.cpp
[AMDGPU][SIOptimizeVGPRLiveRange] Add setpreservesCFG in the legacy pass flow. (#118256)
2024-12-02 23:16:03 +05:30
SIOptimizeVGPRLiveRange.h
[AMDGPU][NewPM] Port SIOptimizeVGPRLiveRange pass to NPM. (#117686)
2024-11-29 09:11:24 +05:30
SIPeepholeSDWA.cpp
[AMDGPU] SIPeepholeSDWA: Disable on existing SDWA instructions (#124131)
2025-01-24 09:12:32 +01:00
SIPeepholeSDWA.h
[AMDGPU][NewPM] Port SIPeepholeSDWA pass to NPM (#107049)
2024-09-11 14:30:16 +04:00
SIPostRABundler.cpp
…
SIPreAllocateWWMRegs.cpp
[AMDGPU] Remove unused includes (NFC) (#116154)
2024-11-13 21:10:03 -08:00
SIPreAllocateWWMRegs.h
[NewPM][AMDGPU] Port SIPreAllocateWWMRegs to NPM (#109939)
2024-10-22 15:37:08 +05:30
SIPreEmitPeephole.cpp
[AMDGPU][SIPreEmitPeephole] Fix mustRetainExeczBranch (#120121)
2024-12-17 11:47:38 +01:00
SIProgramInfo.cpp
[AMDGPU] MCExpr-ify AMDGPU HSAMetadata (#94788)
2024-06-26 16:39:08 +01:00
SIProgramInfo.h
[AMDGPU] MCExpr-ify AMDGPU HSAMetadata (#94788)
2024-06-26 16:39:08 +01:00
SIRegisterInfo.cpp
[AMDGPU] Restore SP from saved-FP or saved-BP (#124007)
2025-01-24 19:13:40 +05:30
SIRegisterInfo.h
Reland [AMDGPU] Serialize WWM_REG vreg flag (#110229) (#112492)
2024-10-21 13:44:09 +05:30
SIRegisterInfo.td
[AMDGPU] Remove Dwarf encodings for subregisters (#117891)
2025-01-06 14:51:16 -05:00
SISchedule.td
AMDGPU: Define new sched model for gfx950 (#117261)
2024-11-22 20:17:52 -08:00
SIShrinkInstructions.cpp
[AMDGPU][True16][MC] true16 for v_fma_f16 (#119477)
2025-01-06 15:02:04 -05:00
SIShrinkInstructions.h
[AMDGPU][NewPM] Port SIShrinkInstructions to new pass manager. (#106967)
2024-09-03 10:52:50 +05:30
SIWholeQuadMode.cpp
[CodeGen][NewPM] Port SIWholeQuadMode to NPM. (#125833)
2025-02-05 18:44:57 +05:30
SIWholeQuadMode.h
[CodeGen][NewPM] Port SIWholeQuadMode to NPM. (#125833)
2025-02-05 18:44:57 +05:30
SMInstructions.td
[AMDGPU] Disallow null for more resource operands (#121941)
2025-01-08 08:02:10 +00:00
SOPInstructions.td
[AMDGPU] Remove s_wakeup_barrier instruction (#122277)
2025-01-10 11:30:22 +01:00
VIInstrFormats.td
…
VINTERPInstructions.td
[AMDGPU][True16][CodeGen] support for true16 for vinterp 16bit instructions (#116702)
2024-12-09 11:52:05 -05:00
VOP1Instructions.td
[AMDGPU][NFC] Simplify t16/fake16 TableGen definitions. (#122693)
2025-01-29 12:46:05 +00:00
VOP2Instructions.td
[AMDGPU][True16][MC][CodeGen] true16 for v_cndmask_b16 (#119736)
2025-01-16 17:18:28 -05:00
VOP3Instructions.td
[AMDGPU][True16][MC] true16 for v_mad_u/i32_u/i16 (#124781)
2025-01-30 12:19:17 -05:00
VOP3PInstructions.td
[AMDGPU][MC] Disallow op_sel in some VOP3P dot instructions (#100485)
2024-12-18 10:50:47 -08:00
VOPCInstructions.td
[AMDGPU][True16][MC] Generate op_sel operands for VOPC instructions (#125561)
2025-02-05 10:40:34 -05:00
VOPDInstructions.td
[AMDGPU] Add GFX12 assembler/disassembler support for v_dual_dot2acc_* (#119211)
2024-12-09 15:12:08 +00:00
VOPInstructions.td
[AMDGPU][True16][CodeGen] true16 codegen for icmp and is_fpclass (#124757)
2025-01-30 12:18:00 -05:00