Files
clang-p2996/llvm/test/CodeGen/AArch64
David Green c552c6c914 [AArch64][GlobalISel] Protect against non-reg operands in matchExtAddvToUdotAddv.
In some situations the first operand to an instruction might not be a register
(for example with intrinsics). We are only interested in extend operations, so
make sure the instruction is one we expect before we attempt to access the
first reg.
2025-02-05 23:57:39 +00:00
..

++ SVE CodeGen Warnings ++

When the WARN check lines fail in the SVE codegen tests it most likely means you
have introduced a warning due to:
1. Adding an invalid call to VectorType::getNumElements() or EVT::getVectorNumElements()
   when the type is a scalable vector.
2. Relying upon an implicit cast conversion from TypeSize to uint64_t.

For generic code, please modify your code to work with ElementCount and TypeSize directly.
For target-specific code that only deals with fixed-width vectors, use the fixed-size interfaces.
Please refer to the code where those functions live for more details.