Philip Reames ed8a6d6155 [RISCV] Add VLA shuffle coverage ...

Add coverage for a few cases which have come up in discussion of
recent VLA shuffle lowering changes.

2025-02-05 18:47:45 -08:00

..

GlobalISel

[AArch64][GlobalISel] Add disjoint handling for add_and_or_is_add. (#123594)

2025-02-02 21:01:49 +00:00

intrinsics

…

rvv

[RISCV] Add VLA shuffle coverage

2025-02-05 18:47:45 -08:00

abds-neg.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

abds.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

abdu-neg.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

abdu.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

add_sext_shl_constant.ll

[RISCV] Added test case for PR119527. NFC (#121816)

2025-01-07 13:33:22 -03:00

add_shl_constant.ll

[RISCV] Don't commute with shift if it would break sh{1,2,3}add pattern (#119527)

2025-01-06 19:23:21 +08:00

add-before-shl.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

add-imm.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

addc-adde-sube-subc.ll

…

addcarry.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

addimm-mulimm.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

addrspacecast.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

aext-to-sext.ll

[TTI][RISCV] Unconditionally break critical edges to sink ADDI (#108889)

2024-11-25 18:59:31 -08:00

aext.ll

…

align-loops.ll

…

align.ll

…

alloca.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

allow-check.ll

…

alu8.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

alu16.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

alu32.ll

…

alu64.ll

…

analyze-branch.ll

…

and-add-lsr.ll

…

and-shl.ll

[RISCV] Optimize (slli (srli (slli X, C1), C1), C2) -> (srli (slli X, C1), C1-C2) (#119567)

2024-12-12 07:58:36 +01:00

and.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

arith-with-overflow.ll

…

atomic-cmpxchg-branch-on-result.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

atomic-cmpxchg-flag.ll

…

atomic-cmpxchg.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

atomic-fence.ll

…

atomic-load-store.ll

[RISCV][ISEL] Lowering to load-acquire/store-release for RISCV Zalasr (#82914)

2024-12-17 00:19:45 -08:00

atomic-rmw-discard.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

atomic-rmw-sub.ll

…

atomic-rmw.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

atomic-signext.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

atomicrmw-cond-sub-clamp.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

atomicrmw-uinc-udec-wrap.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

attributes-module-flag.ll

…

attributes.ll

[RISCV] Renaming muladdi to muliadd as per v0.5 spec. (#124237)

2025-01-27 20:40:45 -08:00

avgceils.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

avgceilu.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

avgfloors.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

avgflooru.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

bf16-promote.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

bfloat-arith.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

bfloat-br-fcmp.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

bfloat-convert.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

bfloat-fcmp.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

bfloat-frem.ll

…

bfloat-imm.ll

…

bfloat-isnan.ll

…

bfloat-mem.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

bfloat-select-fcmp.ll

[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)

2024-09-03 16:04:51 -07:00

bfloat-select-icmp.ll

[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)

2024-09-03 16:04:51 -07:00

bfloat.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

bitextract-mac.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

bitreverse-shift.ll

…

bittest.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

blockaddress.ll

…

branch_zero.ll

…

branch-on-zero.ll

…

branch-opt.ll

…

branch-opt.mir

…

branch-relaxation-rv32.ll

[RISCV][NFC] Split branch-relaxation test

2024-11-12 09:35:16 -08:00

branch-relaxation-rv64.ll

[RISCV][NFC] Split branch-relaxation test

2024-11-12 09:35:16 -08:00

branch.ll

…

bswap-bitreverse.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

bswap-shift.ll

…

byval.ll

…

callee-saved-fpr32s.ll

[RISCV] Enable load clustering by default (#73789)

2024-10-01 13:45:30 +01:00

callee-saved-fpr64s.ll

[RISCV] Enable load clustering by default (#73789)

2024-10-01 13:45:30 +01:00

callee-saved-gprs.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

calling-conv-half.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

calling-conv-ilp32-ilp32f-common.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

calling-conv-ilp32-ilp32f-ilp32d-common.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

calling-conv-ilp32.ll

…

calling-conv-ilp32d.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

calling-conv-ilp32e.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

calling-conv-ilp32f-ilp32d-common.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

calling-conv-lp64-lp64f-common.ll

…

calling-conv-lp64-lp64f-lp64d-common.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

calling-conv-lp64.ll

…

calling-conv-lp64e.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

calling-conv-rv32f-ilp32.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

calling-conv-rv32f-ilp32e.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

calling-conv-sext-zext.ll

…

calling-conv-vector-float.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

calling-conv-vector-on-stack.ll

…

calls.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

clear-cache.ll

…

cm_mvas_mvsa.ll

…

cm_mvas_mvsa.mir

…

cmov-branch-opt.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

cmp-bool.ll

…

codemodel-lowering.ll

[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)

2024-09-26 22:56:12 -07:00

compress-double.ll

…

compress-float.ll

…

compress-inline-asm.ll

…

compress-opt-branch.ll

…

compress-opt-select.ll

Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)

2024-11-26 23:39:45 +08:00

compress.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

condbinops.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

condops.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

convert-highly-predictable-select-to-branch.ll

[RISCV] Rename some Feature* to Tune* (#117966)

2024-11-28 15:01:49 +08:00

copy-frameindex.mir

…

copyprop.ll

…

copysign-casts.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

ctlz-cttz-ctpop.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

ctz_zero_return_test.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

debug-line.ll

[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)

2025-01-28 21:03:12 +05:30

disable-tail-calls.ll

…

disjoint.ll

…

div_minsize.ll

…

div-by-constant.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

div-pow2.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

div.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

double_reduct.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

double-arith-strict.ll

…

double-arith.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

double-bitmanip-dagcombines.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

double-br-fcmp.ll

…

double-calling-conv.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

double-convert-strict.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

double-convert.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

double-fcmp-strict.ll

[RISCV] Enable floating point CSR alias mnemonics for Zfinx. (#108464)

2024-09-12 18:40:52 -07:00

double-fcmp.ll

…

double-frem.ll

…

double-imm.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

double-intrinsics-strict.ll

[RISCV] Add test cases for llvm.tan/asin/acos/atan/atan2/sinh/cosh/tanh. NFC

2024-11-27 10:24:34 -08:00

double-intrinsics.ll

[RISCV] Add test cases for llvm.tan/asin/acos/atan/atan2/sinh/cosh/tanh. NFC

2024-11-27 10:24:34 -08:00

double-isnan.ll

…

double-maximum-minimum.ll

…

double-mem.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

double-previous-failure.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

double-round-conv-sat.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

double-round-conv.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

double-select-fcmp.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

double-select-icmp.ll

…

double-stack-spill-restore.ll

…

double-zfa.ll

[RISCV] f32 roundeven pattern missed for Zfa (#118672)

2024-12-04 13:52:20 -08:00

dso_local_equivalent.ll

…

dwarf-eh.ll

…

early-clobber-tied-def-subreg-liveness.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

eh-dwarf-cfa.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

elf-preemption.ll

…

emutls.ll

…

exception-pointer-register.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

fastcc-bf16.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fastcc-float.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fastcc-half.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fastcc-int.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fastcc-without-f-reg.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

features-info.ll

[RISCV] Add support of Sdext,Sdtrig extentions (#120936)

2025-01-03 17:25:42 +08:00

fixed-csr.ll

[RISCV][MRI] Account for fixed registers when determining callee saved regs (#115756)

2024-12-06 14:07:27 -05:00

fixups-diff.ll

…

fli-licm.ll

…

float-arith-strict.ll

…

float-arith.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

float-bit-preserving-dagcombines.ll

…

float-bitmanip-dagcombines.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

float-br-fcmp.ll

…

float-convert-strict.ll

[RISCV] Add some Zfinx instructions to hasAllNBitUsers.

2024-08-08 17:33:54 -07:00

float-convert.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

float-fcmp-strict.ll

[RISCV] Enable floating point CSR alias mnemonics for Zfinx. (#108464)

2024-09-12 18:40:52 -07:00

float-fcmp.ll

…

float-frem.ll

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

2024-10-01 22:09:27 -07:00

float-imm.ll

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

2024-10-01 22:09:27 -07:00

float-intrinsics-strict.ll

[RISCV] Add test cases for llvm.tan/asin/acos/atan/atan2/sinh/cosh/tanh. NFC

2024-11-27 10:24:34 -08:00

float-intrinsics.ll

[RISCV] Add test cases for llvm.tan/asin/acos/atan/atan2/sinh/cosh/tanh. NFC

2024-11-27 10:24:34 -08:00

float-isnan.ll

…

float-maximum-minimum.ll

[LegalizeTypes] Support softening FMINIMUM/FMAXIMUM (#115463)

2024-11-09 10:02:06 +00:00

float-mem.ll

…

float-round-conv-sat.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

float-round-conv.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

float-select-fcmp.ll

…

float-select-icmp.ll

…

float-select-verify.ll

…

float-zfa.ll

[RISCV] f32 roundeven pattern missed for Zfa (#118672)

2024-12-04 13:52:20 -08:00

flt-rounds.ll

…

fmax-fmin.ll

…

fold-addi-loadstore.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

fold-binop-into-select-return-constant.ll

…

fold-binop-into-select.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

forced-atomics.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

fp16-promote.ll

…

fp128.ll

[RuntimeLibcalls] Fix spelling fminmum->fminimum fmaxmum->fmaximum. (#118728)

2024-12-06 20:28:53 -08:00

fp-fcanonicalize.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

fpclamptosat.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

fpenv.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

frame-info.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

frame.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

frameaddr-returnaddr.ll

…

frm-dependency.ll

…

get-register-invalid.ll

…

get-register-noreserve.ll

…

get-register-reserve.ll

…

get-setcc-result-type.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

ghccc-nest.ll

…

ghccc-rv32.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

ghccc-rv64.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

ghccc-without-f-reg.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

global-merge-minsize-smalldata-nonzero.ll

[RISCV] Enable merging of external globals by default (#117880)

2024-12-11 16:06:49 +00:00

global-merge-minsize-smalldata-zero.ll

[RISCV] Enable merging of external globals by default (#117880)

2024-12-11 16:06:49 +00:00

global-merge-minsize.ll

[RISCV] Enable merging of external globals by default (#117880)

2024-12-11 16:06:49 +00:00

global-merge-offset.ll

[RISCV] Enable merging of external globals by default (#117880)

2024-12-11 16:06:49 +00:00

global-merge.ll

[RISCV] Enable merging of external globals by default (#117880)

2024-12-11 16:06:49 +00:00

graalcc.ll

…

half-arith-strict.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

half-arith.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

half-bitmanip-dagcombines.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

half-br-fcmp.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

half-convert-strict.ll

[LegalizeTypes][RISCV][X86] Legalize FP_ROUND to libcall in SoftPromoteHalfRes_FP_ROUND if the input type is softened. (#119481)

2024-12-10 22:21:49 -08:00

half-convert.ll

[LegalizeTypes][RISCV][X86] Legalize FP_ROUND to libcall in SoftPromoteHalfRes_FP_ROUND if the input type is softened. (#119481)

2024-12-10 22:21:49 -08:00

half-fcmp-strict.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

half-fcmp.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

half-frem.ll

…

half-imm.ll

[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)

2024-09-26 22:56:12 -07:00

half-intrinsics.ll

[RISCV] Add test cases for llvm.tan/asin/acos/atan/atan2/sinh/cosh/tanh. NFC

2024-11-27 10:24:34 -08:00

half-isnan.ll

…

half-maximum-minimum.ll

…

half-mem.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

half-round-conv-sat.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

half-round-conv.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

half-select-fcmp.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

half-select-icmp.ll

[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)

2024-09-03 16:04:51 -07:00

half-zfa-fli.ll

…

half-zfa.ll

[RISCV] f32 roundeven pattern missed for Zfa (#118672)

2024-12-04 13:52:20 -08:00

hoist-global-addr-base.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

hwasan-check-memaccess.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

i32-icmp.ll

…

i64-icmp.ll

…

iabs.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

idiv_large.ll

…

imm-cse.ll

…

imm.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

indirectbr.ll

…

init-array.ll

…

inline-asm-abi-names.ll

…

inline-asm-clobbers.ll

…

inline-asm-d-abi-names.ll

…

inline-asm-d-constraint-f.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

inline-asm-d-modifier-N.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

inline-asm-f-abi-names.ll

…

inline-asm-f-constraint-f.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

inline-asm-f-modifier-N.ll

[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)

2024-10-18 10:40:38 +01:00

inline-asm-i-constraint-i1.ll

…

inline-asm-invalid.ll

[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)

2024-10-18 10:40:38 +01:00

inline-asm-mem-constraint-2.ll

[test][RISCV] Precommit inline asm tests for #104925

2024-08-26 13:30:23 +03:00

inline-asm-mem-constraint.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

inline-asm-s-constraint-error.ll

…

inline-asm-s-constraint.ll

…

inline-asm-v-constraint.ll

[RISCV] Clear vill for whole vector register moves in vsetvli insertion (#118283)

2024-12-06 00:48:05 +08:00

inline-asm-xsfvcp.ll

[RISCV][VCIX] Add vcix_state to GNU inline assembly register set (#106914)

2024-09-30 23:52:35 -07:00

inline-asm-zdinx-constraint-r.ll

[RISCV] Support inline assembly 'f' constraint for Zfinx. (#112986)

2024-10-18 18:17:23 -07:00

inline-asm-zfh-constraint-f.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

inline-asm-zfh-modifier-N.ll

[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)

2024-10-18 10:40:38 +01:00

inline-asm-zfinx-constraint-r.ll

[RISCV] Support inline assembly 'f' constraint for Zfinx. (#112986)

2024-10-18 18:17:23 -07:00

inline-asm-zhinx-constraint-r.ll

[RISCV] Support inline assembly 'f' constraint for Zfinx. (#112986)

2024-10-18 18:17:23 -07:00

inline-asm.ll

[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)

2024-10-18 10:40:38 +01:00

inline-option-directive.ll

…

instruction-count-remark.mir

[CodeGen] Fix InstructionCount remarks for MI bundles (#107621)

2024-10-02 13:37:25 -07:00

interrupt-attr-args-error.ll

…

interrupt-attr-callee.ll

…

interrupt-attr-invalid.ll

…

interrupt-attr-nocall.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

interrupt-attr-ret-error.ll

…

interrupt-attr.ll

…

intrinsic-cttz-elts-vscale.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

intrinsic-cttz-elts.ll

…

ipra.ll

[RISCV] Implement getIPRACSRegs hook (#125586)

2025-02-04 10:02:42 -03:00

isel-optnone.ll

…

jumptable-swguarded.ll

[LegalizeDAG] Use Base+Offset instead of Offset+Base for jump tables

2025-01-31 14:05:34 -08:00

jumptable.ll

[LegalizeDAG] Use Base+Offset instead of Offset+Base for jump tables

2025-01-31 14:05:34 -08:00

kcfi-isel-mir.ll

[RISCV] Add call preserved regmask to tail calls. (#122181)

2025-01-08 16:19:31 -08:00

kcfi-mir.ll

[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)

2025-01-28 21:03:12 +05:30

kcfi-patchable-function-prefix.ll

…

kcfi.ll

…

lack-of-signed-truncation-check.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

large-stack.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

legalize-fneg.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

libcall-tail-calls.ll

…

lit.local.cfg

…

live-sp.mir

[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)

2025-01-28 21:03:12 +05:30

llvm.exp10.ll

[RISCV] Move scalar llvm.exp10 tests into half/float/double-intrinsics.ll. NFC

2024-11-27 10:24:33 -08:00

llvm.frexp.ll

[SDAG] Allow folding stack slots into sincos/frexp in more cases (#118117)

2024-12-17 10:54:17 +00:00

load-setcc-combine.ll

…

local-stack-slot-allocation.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

loop-strength-reduce-add-cheaper-than-mul.ll

…

loop-strength-reduce-loop-invar.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

lpad.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

lsr-legaladdimm.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

machine-combiner-mir.ll

…

machine-combiner-strategies.ll

…

machine-combiner.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

machine-combiner.mir

…

machine-cp.mir

…

machine-cse.ll

…

machine-outliner-and-machine-copy-propagation.ll

…

machine-outliner-call.ll

Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)

2024-11-26 23:39:45 +08:00

machine-outliner-cfi.mir

Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)

2024-11-26 23:39:45 +08:00

machine-outliner-leaf-descendants.ll

Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)

2024-11-26 23:39:45 +08:00

machine-outliner-patchable.ll

Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)

2024-11-26 23:39:45 +08:00

machine-outliner-position.mir

Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)

2024-11-26 23:39:45 +08:00

machine-outliner-throw.ll

…

machine-pipeliner.ll

[RISCV] Add software pipeliner support (#117546)

2024-12-19 13:00:08 +08:00

machine-sink-load-immediate.ll

[TTI][RISCV] Unconditionally break critical edges to sink ADDI (#108889)

2024-11-25 18:59:31 -08:00

machinelicm-address-pseudos.ll

[RISCV] Add register allocation hints for lui/auipc+addi fusion. (#123860)

2025-01-27 11:16:22 -08:00

machinelicm-constant-phys-reg.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

machineoutliner-jumptable.mir

…

machineoutliner-pcrel-lo.mir

[RISCV] Don't outline pcrel_lo when the function has a section prefix (#107943)

2024-09-11 09:53:11 -07:00

machineoutliner-x5.mir

Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)

2024-11-26 23:39:45 +08:00

machineoutliner.mir

Reapply "[RISCV] Implement tail call optimization in machine outliner" (#117700)

2024-11-26 23:39:45 +08:00

MachineSink-implicit-x0.mir

…

macro-fusion-lui-addi.ll

[RISCV] Add register allocation hints for lui/auipc+addi fusion. (#123860)

2025-01-27 11:16:22 -08:00

macro-fusions.mir

…

make-compressible-for-store-address.mir

…

make-compressible-rv64.mir

…

make-compressible-zbc-zhinx.mir

[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)

2024-09-26 22:56:12 -07:00

make-compressible-zbc.mir

[RISCV] Fix IR for store_large_offset_no_opt_i16 in make-compressible-zbc.mir. NFC

2024-09-16 12:51:07 -07:00

make-compressible-zfinx.mir

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

2024-10-01 22:09:27 -07:00

make-compressible.mir

…

mem64.ll

…

mem.ll

…

memcmp-optsize.ll

[RISCV] Re-generate memcmp test checks missed in #121530. NFC

2025-01-03 09:48:41 -08:00

memcmp.ll

[ExpandMemCmp] Recognize canonical form of (icmp sle/sge X, 0) in getMemCmpOneBlock. (#121540)

2025-01-03 10:23:13 -08:00

memcpy-inline.ll

…

memcpy.ll

Reapply "[RISCV] Rework memcpy test (#120364)"

2025-01-13 12:06:26 +08:00

memmove.ll

[RISCV] Add test coverage for memmove (#120232)

2025-02-05 14:42:38 +08:00

memset-inline.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

memset-pattern.ll

Reapply [IR] Initial introduction of llvm.experimental.memset_pattern (#97583)

2024-11-15 15:21:39 +00:00

min-max.ll

…

mir-target-flags.ll

…

misched-load-clustering.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

misched-mem-clustering.mir

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

misched-postra-direction.mir

CodeGen][NewPM] Port MachineScheduler to NPM. (#125703)

2025-02-05 12:17:59 +05:30

miss-sp-restore-eh.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

module-elf-flags.ll

…

module-target-abi2.ll

…

module-target-abi3.ll

…

module-target-abi.ll

…

mul.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

musttail-call.ll

…

naked-fn-with-frame-pointer.ll

[llvm] Consistently respect naked fn attribute in TargetFrameLowering::hasFP() (#106014)

2024-10-18 09:35:42 +04:00

narrow-shl-cst.ll

…

neg-abs.ll

[DAGCombiner] Turn (neg (max x, (neg x))) into (min x, (neg x)) (#120666)

2025-01-02 16:28:55 -08:00

nest-register.ll

…

nomerge.ll

…

nontemporal-scalable.ll

…

nontemporal.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

O0-pipeline.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

O3-pipeline.ll

[PartiallyInlineLibCalls] Add infrastructure for emitting optimization remarks from PartiallyInlineLibCalls (#122654)

2025-01-22 13:15:40 +07:00

opt-w-instrs.mir

[RISCV] Add PseudoCCMOVGPRNoX0 test caes for RISCVOptWInstrs. NFC

2025-01-31 15:19:44 -08:00

option-nopic.ll

…

option-norelax.ll

…

option-norvc.ll

…

option-pic.ll

…

option-relax-relocation.ll

…

option-relax.ll

…

option-rvc.ll

…

optnone-store-no-combine.ll

…

or-is-add.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

orc-b-patterns.ll

[RISCV] Re-generate orc-b-patterns.ll for store clustering. NFC

2024-10-11 14:28:51 -07:00

out-of-reach-emergency-slot.mir

[RISCV] fix SP recovery in a function epilogue (#110809)

2024-10-04 12:22:11 +03:00

overflow-intrinsic-optimizations.ll

…

overflow-intrinsics.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

patchable-function-entry.ll

…

pei-crash.ll

…

pic-models.ll

…

pr40333.ll

…

pr51206.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

pr53662.mir

…

pr55201.ll

…

pr56110.ll

…

pr56457.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

pr58025.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

pr58286.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

pr58511.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

pr63365.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

pr63816.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

pr64503.ll

…

pr64645.ll

…

pr64772.ll

…

pr64935.ll

…

pr65025.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

pr66603.ll

…

pr68855.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

pr69586.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

pr80052.mir

…

pr84200.ll

…

pr84653_pr85190.ll

[RISCV] Select and/or/xor with certain constants to Zbb ANDN/ORN/XNOR (#120221)

2024-12-19 21:38:20 +01:00

pr88365.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

pr90652.ll

…

pr90730.ll

…

pr92193.ll

…

pr94145.ll

…

pr94265.ll

…

pr95271.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

pr95284.ll

[DAG] SimplifyMultipleUseDemandedBits - ignore SRL node if we're just demanding known sign bits (#114389)

2024-10-31 16:40:29 +00:00

pr96366.ll

…

pr97304.ll

[RISCV] Add correct MachinePointerInfo when putting arguments on the stack. (#110140)

2024-09-27 13:48:01 -07:00

prefer-w-inst.ll

…

prefer-w-inst.mir

…

prefetch.ll

…

prolog-epilogue.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

push-pop-opt-crash.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

push-pop-popret.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

rda-stack.mir

[ReachingDefAnalysis] Fix management of MBBFrameObjsReachingDefs (#124943)

2025-02-04 10:04:19 -05:00

readcyclecounter.ll

…

readsteadycounter.ll

…

reduce-unnecessary-extension.ll

…

reduction-formation.ll

[RISCV] Enable load clustering by default (#73789)

2024-10-01 13:45:30 +01:00

redundant-copy-from-tail-duplicate.ll

[RISCV] Add reductions to list of roots in tryToReduceVL (#107595)

2024-09-10 18:47:20 -07:00

regalloc-last-chance-recoloring-failure.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

relax-per-target-feature.ll

…

rem.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

remat.ll

…

renamable-copy.mir

[TII][RISCV] Add renamable bit to copyPhysReg (#91179)

2024-08-27 10:08:43 +08:00

repeated-fp-divisors.ll

…

replace-with-veclib-sleef-scalable.ll

[RISCV][SLEEF]: Support SLEEF vector library for RISC-V target. (#114014)

2024-11-26 12:25:54 +03:00

reserved-reg-errors.ll

…

reserved-regs.ll

…

riscv-codegen-prepare-atp.ll

[RISCV] Implement RISCVTTIImpl::shouldConsiderAddressTypePromotion for RISCV (#102560)

2024-08-15 10:37:04 +08:00

riscv-codegenprepare-asm.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

riscv-codegenprepare.ll

…

riscv-func-target-feature.ll

…

riscv-tail-dup-size.ll

…

rotl-rotr.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

rv32-fuchsia.ll

…

rv32-inline-asm-pairs.ll

[RISCV] Support cR Inline Asm Constraint (#124174)

2025-01-23 16:19:19 -08:00

rv32e.ll

…

rv32i-rv64i-float-double.ll

…

rv32i-rv64i-half.ll

…

rv32xtheadba.ll

[RISCV] Fix XTheadba patterns broken since cfc574a6cd.

2024-12-26 21:50:35 -08:00

rv32xtheadbb.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

rv32xtheadbs.ll

…

rv32zba.ll

[RISCV] Zba testing improvements. NFC

2024-11-14 13:47:49 -08:00

rv32zbb-intrinsic.ll

…

rv32zbb-zbkb.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

rv32zbb.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

rv32zbc-intrinsic.ll

…

rv32zbc-zbkc-intrinsic.ll

…

rv32zbkb-intrinsic.ll

…

rv32zbkb.ll

…

rv32zbkx-intrinsic.ll

…

rv32zbs.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

rv32zimop-intrinsic.ll

…

rv32zknd-intrinsic-autoupgrade.ll

…

rv32zknd-intrinsic.ll

…

rv32zkne-intrinsic-autoupgrade.ll

…

rv32zkne-intrinsic.ll

…

rv32zknh-intrinsic.ll

…

rv32zksed-intrinsic-autoupgrade.ll

…

rv32zksed-intrinsic.ll

…

rv32zksh-intrinsic.ll

…

rv64-double-convert-strict.ll

[RISCV] Add test cases for RV64 i128<->half/float/double (#115124)

2024-11-06 11:36:30 -08:00

rv64-double-convert.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

rv64-float-convert-strict.ll

[LegalizeTypes][RISCV] Call setTypeListBeforeSoften from ExpandIntRes_FP_TO_XINT if the FP type needs to be softened (#118269)

2024-12-02 09:06:08 -08:00

rv64-float-convert.ll

[LegalizeTypes][RISCV] Call setTypeListBeforeSoften from ExpandIntRes_FP_TO_XINT if the FP type needs to be softened (#118269)

2024-12-02 09:06:08 -08:00

rv64-half-convert-strict.ll

[LegalizeTypes][RISCV] Call setTypeListBeforeSoften from ExpandIntRes_FP_TO_XINT if the FP type needs to be softened (#118269)

2024-12-02 09:06:08 -08:00

rv64-half-convert.ll

[LegalizeTypes][RISCV] Call setTypeListBeforeSoften from ExpandIntRes_FP_TO_XINT if the FP type needs to be softened (#118269)

2024-12-02 09:06:08 -08:00

rv64-inline-asm-pairs.ll

[RISCV] Support cR Inline Asm Constraint (#124174)

2025-01-23 16:19:19 -08:00

rv64-large-stack.ll

…

rv64-patchpoint.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

rv64-stackmap-args.ll

[CodeGen] @llvm.experimental.stackmap make operands immediate (#117932)

2024-12-11 17:41:19 +08:00

rv64-stackmap-frame-setup.ll

…

rv64-stackmap-nops.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

rv64-stackmap.ll

…

rv64-statepoint-call-lowering-x1.ll

…

rv64-statepoint-call-lowering-x2.ll

…

rv64-statepoint-call-lowering.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

rv64-trampoline.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

rv64-typepromotion.ll

…

rv64d-double-convert-strict.ll

[RISCV] Add Zfinx/Zdinx RUN lines to rv64d-double-convert-strict.ll and rv64f-float-convert-strict.ll. NFC

2024-11-05 21:48:38 -08:00

rv64d-double-convert.ll

[RISCV] Add Zdinx RUN line to rv64d-double-convert.ll. NFC

2024-11-05 21:12:09 -08:00

rv64e.ll

…

rv64f-float-convert-strict.ll

[RISCV] Add Zfinx/Zdinx RUN lines to rv64d-double-convert-strict.ll and rv64f-float-convert-strict.ll. NFC

2024-11-05 21:48:38 -08:00

rv64f-float-convert.ll

…

rv64i-complex-float.ll

…

rv64i-demanded-bits.ll

…

rv64i-double-softfloat.ll

…

rv64i-exhaustive-w-insts.ll

…

rv64i-shift-sext.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

rv64i-single-softfloat.ll

…

rv64i-tricky-shifts.ll

…

rv64i-w-insts-legalization.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

rv64m-exhaustive-w-insts.ll

…

rv64m-w-insts-legalization.ll

[TTI][RISCV] Unconditionally break critical edges to sink ADDI (#108889)

2024-11-25 18:59:31 -08:00

rv64xtheadba.ll

[RISCV] Use add_like_non_imm12 in XTheadba patterns to match Zba.

2024-12-29 12:39:37 -08:00

rv64xtheadbb.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

rv64xtheadbs.ll

…

rv64zba.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

rv64zbb-intrinsic.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

rv64zbb-zbkb.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

rv64zbb.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

rv64zbc-intrinsic.ll

…

rv64zbc-zbkc-intrinsic.ll

…

rv64zbkb-intrinsic.ll

…

rv64zbkb.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

rv64zbkx-intrinsic.ll

…

rv64zbs.ll

[RISCV][DAGCombine] Combine sext_inreg (shl X, Y), i32 into sllw X, Y (#111101)

2024-10-04 16:03:09 +08:00

rv64zfh-half-convert-strict.ll

…

rv64zfh-half-convert.ll

[RISCV] Don't combine (sext_inreg (fmv_x_anyexth X), i16) with Zhinx.

2024-08-14 15:18:10 -07:00

rv64zfh-half-intrinsics.ll

…

rv64zfhmin-half-convert-strict.ll

[RISCV] Custom promote f16/bf16 (s/u)int_to_fp. (#107026)

2024-09-03 13:33:14 -07:00

rv64zfhmin-half-convert.ll

[RISCV] Custom promote f16/bf16 (s/u)int_to_fp. (#107026)

2024-09-03 13:33:14 -07:00

rv64zfhmin-half-intrinsics.ll

…

rv64zimop-intrinsic.ll

…

rv64zknd-intrinsic.ll

…

rv64zknd-zkne-intrinsic.ll

…

rv64zkne-intrinsic.ll

…

rv64zknh-intrinsic-autoupgrade.ll

…

rv64zknh-intrinsic.ll

…

rv64zksed-intrinsic-autoupgrade2.ll

…

rv64zksed-intrinsic-autoupgrade.ll

…

rv64zksed-intrinsic.ll

…

rv64zksh-intrinsic-autoupgrade.ll

…

rv64zksh-intrinsic.ll

…

sadd_sat_plus.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

sadd_sat.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

saverestore-scs.ll

…

saverestore.ll

…

scmp.ll

[RISCV] Enable load clustering by default (#73789)

2024-10-01 13:45:30 +01:00

sdata-limit-0.ll

…

sdata-limit-4.ll

…

sdata-limit-8.ll

…

sdata-local-sym.ll

…

sdata-sections.ll

[RISCV] Let -data-sections also work on sbss/sdata sections (#87040)

2024-08-23 14:06:12 +01:00

sdiv-pow2-cmov.ll

…

select-and.ll

[RISCV] Add MIPS extensions (#121394)

2025-01-28 08:04:09 +01:00

select-bare.ll

[RISCV] Add MIPS extensions (#121394)

2025-01-28 08:04:09 +01:00

select-binop-identity.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

select-cc.ll

[RISCV] Add MIPS extensions (#121394)

2025-01-28 08:04:09 +01:00

select-const.ll

[RISCV] Add Zicond run lines to select-const.ll. NFC

2025-02-05 15:32:22 -08:00

select-constant-xor.ll

…

select-optimize-multiple.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

select-optimize-multiple.mir

…

select-or.ll

[RISCV] Add MIPS extensions (#121394)

2025-01-28 08:04:09 +01:00

select-to-and-zext.ll

…

select.ll

[TTI][RISCV] Unconditionally break critical edges to sink ADDI (#108889)

2024-11-25 18:59:31 -08:00

selectcc-to-shiftand.ll

[RISCV] Limit (and (sra x, c2), c1) -> (srli (srai x, c2-c3), c3) isel in some cases. (#102034)

2024-08-06 20:27:14 -07:00

setcc-logic.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

sext-zext-trunc.ll

…

sextw-removal-debug.mir

…

sextw-removal.ll

[TTI][RISCV] Unconditionally break critical edges to sink ADDI (#108889)

2024-11-25 18:59:31 -08:00

shadowcallstack.ll

[RISCV] Separate HW/SW shadow stack on RISC-V (#112478)

2024-11-08 00:16:45 +08:00

shift-amount-mod.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

shift-and.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

shift-masked-shamt.ll

…

shifts.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

shl-cttz.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

shl-demanded.ll

…

shlimm-addimm.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

short-forward-branch-opt.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

shrinkwrap-jump-table.ll

[LegalizeDAG] Use Base+Offset instead of Offset+Base for jump tables

2025-01-31 14:05:34 -08:00

shrinkwrap.ll

[RISCV] Add shrinkwrap test cases showing gaps in current impl

2024-11-27 11:14:51 -08:00

sifive7-enable-intervals.mir

[MISched] Unify the way to specify scheduling direction (#119518)

2024-12-12 11:24:07 +08:00

signbit-test.ll

…

signed-truncation-check.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

sink-and-fold-crash.mir

…

sink-icmp.ll

…

spill-fill-fold.ll

…

spill-fpr-scalar.ll

…

spir-kernel-cc.ll

…

split-offsets.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

split-sp-adjust.ll

…

split-store.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

split-udiv-by-constant.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

split-urem-by-constant.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

srem-lkk.ll

…

srem-seteq-illegal-types.ll

[RISCV][VLOPT] Enable the RISCVVLOptimizer by default (#119461)

2024-12-17 16:19:35 -05:00

srem-vector-lkk.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

srodata.ll

…

ssub_sat_plus.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

ssub_sat.ll

…

stack-clash-prologue-nounwind.ll

[RISCV] Compute liveins for new basic blocks in emitStackProbeInline.

2024-12-10 12:37:45 -08:00

stack-clash-prologue.ll

[RISCV] Stack clash protection for dynamic alloca (#122508)

2025-01-16 11:58:42 -08:00

stack-folding.ll

…

stack-guard-global.ll

[RISCV] Support -mstack-protector-guard=tls (#108942)

2024-10-02 16:33:31 -07:00

stack-guard-tls.ll

[RISCV] Support -mstack-protector-guard=tls (#108942)

2024-10-02 16:33:31 -07:00

stack-inst-compress.mir

[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)

2025-01-28 21:03:12 +05:30

stack-offset.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

stack-protector-target.ll

…

stack-realignment-with-variable-sized-objects.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

stack-realignment.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

stack-slot-coloring.mir

…

stack-slot-size.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

stack-store-check.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

subtarget-features-std-ext.ll

…

switch-width.ll

…

tagged-globals.ll

…

tail-calls.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

target-abi-invalid.ll

…

target-abi-valid.ll

…

thread-pointer.ll

…

tls-models.ll

…

tlsdesc-symbol.ll

…

trunc-free.ll

…

trunc-nsw-nuw.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

typepromotion-overflow.ll

[TTI][RISCV] Unconditionally break critical edges to sink ADDI (#108889)

2024-11-25 18:59:31 -08:00

uadd_sat_plus.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

uadd_sat.ll

…

ucmp.ll

[RISCV] Enable load clustering by default (#73789)

2024-10-01 13:45:30 +01:00

umulo-128-legalisation-lowering.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

unaligned-load-store.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

unfold-masked-merge-scalar-variablemask.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

unroll-loop-cse.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

urem-lkk.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

urem-seteq-illegal-types.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

urem-vector-lkk.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

usub_sat_plus.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

usub_sat.ll

…

vararg-ilp32e.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

vararg.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

varargs-with-fp-and-second-adj.ll

[RISCV] fix SP recovery in varargs functions (#114316)

2024-11-06 19:30:32 +03:00

vector-abi.ll

…

vector-tuple-zeroinitializer.ll

[RISCV] Handle zeroinitializer of vector tuple Type (#113995)

2024-12-04 13:40:02 +08:00

verify-instr.mir

…

vlenb.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

vscale-demanded-bits.ll

Move stepvector intrinsic out of experimental namespace (#98043)

2024-08-28 12:48:20 +01:00

wide-mem.ll

…

wide-scalar-shift-by-byte-multiple-legalization.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

wide-scalar-shift-legalization.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

xaluo.ll

[TargetLowering] Improve one signature of forceExpandWideMUL. (#123991)

2025-01-23 12:49:35 -08:00

xcvalu.ll

[RISCV] Implement Clang Builtins for XCValu Extension in CV32E40P (#100684)

2024-10-01 11:22:02 +10:00

xcvbi.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

xcvbitmanip.ll

…

xcvmac.ll

…

xcvmem-heuristic.ll

[RISCV] Implement RISCVTTIImpl::getPreferredAddressingMode for HasVendorXCVmem (#120533)

2024-12-31 10:56:28 +08:00

xcvmem.ll

…

xray-attribute-instrumentation.ll

[XRay][RISCV] RISCV support for XRay (#117368)

2024-12-10 17:57:04 -08:00

xtheadfmemidx.ll

…

xtheadmac.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

xtheadmemidx.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

xtheadmempair.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

zbb-cmp-combine.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

zbb-logic-neg-imm.ll

[RISCV] Enable Zbb ANDN/ORN/XNOR for more 64-bit constants (#122698)

2025-01-14 09:15:14 +01:00

zcb-regalloc-hints.ll

…

zcmp-additional-stack.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

zcmp-cm-popretz.mir

[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)

2025-01-28 21:03:12 +05:30

zcmp-cm-push-pop.mir

[RISC-V] Fix incorrect epilogue_begin setting in debug line table (#120623)

2025-01-28 21:03:12 +05:30

zcmp-prolog-epilog-crash.mir

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

zcmp-with-float.ll

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

zdinx-asm-constraint.ll

[RISCV] Support cR Inline Asm Constraint (#124174)

2025-01-23 16:19:19 -08:00

zdinx-boundary-check.ll

[RISCV] Enable bidirectional scheduling and tracking register pressure (#115445)

2024-11-15 17:53:14 +08:00

zdinx-large-spill.mir

[RISCV][CFI] add function epilogue cfi information (#110810)

2024-11-06 00:20:21 +03:00

zdinx-memoperand.ll

[RISCV] Support multiple memory operands in expandRV32ZdinxStore.

2025-01-27 22:10:51 -08:00

zext-with-load-is-free.ll

…

zfh-half-intrinsics-strict.ll

[SelectionDAG][RISCV][AArch64] Allow f16 STRICT_FLDEXP to be promoted. Fix integer promotion of STRICT_FLDEXP in type legalizer. (#117633)

2024-11-25 16:12:45 -08:00

zfh-half-intrinsics.ll

…

zfhmin-half-intrinsics-strict.ll

[SelectionDAG][RISCV][AArch64] Allow f16 STRICT_FLDEXP to be promoted. Fix integer promotion of STRICT_FLDEXP in type legalizer. (#117633)

2024-11-25 16:12:45 -08:00

zfhmin-half-intrinsics.ll

[RISCV] Add test for llvm.round.i32.f16 RV64+Zfhmin/Zhinxmin. NFC

2024-09-01 12:15:00 -07:00

zfhmin-imm.ll

…

zicfilp-indirect-branch.ll

…

zmmul.ll

…